tag: noise

Quantum Issues And Progress
By Katherine Derbyshire - 07 Jan, 2019 - Comments: 3

Quantum computing is showing significant promise, and research is beginning to move from the earliest stages to a deeper understanding of what works best commercially and why. On paper, quantum computing algorithms are potentially revolutionary. They suggest a way to solve some problems more quickly and more accurately than conventional computers ever could. But out in the real world of prac... » read more

How Much Data Can Be Pushed Through Copper Wires?
By Jeff McGuire - 08 Oct, 2018 - Comments: 0

As the amount of digital data grows, so do requirements on the speed of the transmission at all levels of the transmission chain—between dies in a shared package, between packaged chips inside a device, and between devices. The communication channels encountered at every stage of this communication are different in nature. Those between dies in a shared package, or between packaged chips in a... » read more

High-Speed SerDes At 7nm
By Ed Sperling - 30 Jul, 2018 - Comments: 0

eSilicon’s David Axelrad discusses the challenges with 56Gbps and 112Gps SerDes, and why the switch from analog to digital is required for performance and low power. https://youtu.be/E-CU8TLvjjc » read more

The Growing Materials Challenge
By Katherine Derbyshire - 11 Jun, 2018 - Comments: 0

By Katherine Derbyshire & Ed Sperling Materials have emerged as a growing challenge across the semiconductor supply chain, as chips continue to scale, or as they are utilized in new devices such as sensors for AI or machine learning systems. Engineered materials are no longer optional at advanced nodes. They are now a requirement, and the amount of new material content in chips contin... » read more

Analog Migration Equals Redesign
By Ann Mutschler - 24 May, 2018 - Comments: 1

Analog design has never been easy. Engineers can spend their entire careers focused just on phase-locked loops (PLLs), because to get them right the functionality of circuits need to be understood in depth, including how they respond across different process corners and different manufacturing processes. In the finFET era, those challenges have only intensified for analog circuits. Reuse, fo... » read more

Electromagnetic Crosstalk Considerations In Low Power Designs
By Magdy Abadir - 19 May, 2018 - Comments: 0

By Magdy Abadir, Padelis Papadopoulos, and Yehea Ismail
 Power consumption continues to be a critical design metric in high-performance mobile electronics. In order to meet the aggressive power budget targets, chips today need to operate at extremely low power levels, which increases the critical signals’ susceptibility to electromagnetic (EM) crosstalk effects. Because a low-power So... » read more

The Power Of De-Integration
By Ed Sperling - 17 May, 2018 - Comments: 0

The idea that more functionality can be added into a single chip, or even into a single system, is falling out of vogue. For an increasing number of applications, it's no longer considered the best option for boosting performance or lowering power, and it costs too much. Hooman Moshar, vice president of engineering at Broadcom, said in a keynote speech at Mentor's User2User conference this w... » read more

Designing 5G Chips
By Ann Mutschler - 18 Apr, 2018 - Comments: 0

5G is the wireless technology of the future, and it’s coming fast. The technology boasts very high-speed data transfer rates, much lower latency than 4G LTE, and the ability to handle significantly higher densities of devices per cell site. In short, it is the best technology for the massive amount of data that will be generated by sensors in cars, IoT devices, and a growing list of next-g... » read more

IP Electromagnetic Crosstalk Requires Contextual Signoff
By Magdy Abadir - 16 Apr, 2018 - Comments: 0

By Magdy Abadir and Anand Raman Continuous advancement in technology scaling is enabling the emergence of high-performance application markets such as artificial intelligence, autonomous cars and 5G communication. These electronic systems operate at multi-GHz speed, while consuming the lowest amount of power possible leaving very little margin for error. Chips in these systems are highly in... » read more

Tech Talk: 5/3nm Parasitics
By Ed Sperling - 22 Feb, 2018 - Comments: 0

Ralph Iverson, principal R&D engineer at Synopsys, talks about parasitic extraction at 5/3nm and what to expect with new materials and gate structures such as gate-all-around FETs and vertical nanowire FETs. https://youtu.be/24C6byQBkuI » read more

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