Why It’s So Difficult — And Costly — To Secure Chips

By Ed Sperling - 02 Dec, 2021 - Comments: 0

Rising concerns about the security of chips used in everything from cars to data centers are driving up the cost and complexity of electronic systems in a variety of ways, some obvious and others less so. Until very recently, semiconductor security was viewed more as a theoretical threat than a real one. Governments certainly worried about adversaries taking control of secure systems through... » read more

Debugging Embedded Applications

By Ann Mutschler - 10 Nov, 2021 - Comments: 0

Debugging embedded designs is becoming increasingly difficult as the number of observed and possible interactions between hardware and software continue to grow, and as more features are crammed into chips, packages, and systems. But there also appear to be some advances on this front, involving a mix of techniques, including hardware trace, scan chain-based debug, along with better simulation ... » read more

Complex Chips Make Security More Difficult

By John Koon - 04 Nov, 2021 - Comments: 0

Semiconductor supply chain management is becoming more complex with many more moving parts as chips become increasingly disaggregated, making it difficult to ensure where parts originated and whether they have been compromised before they are added into advanced chips or packages. In the past, supply chain concerns largely focused primarily on counterfeit parts or gray-market substitutions u... » read more

High-Level Synthesis For RISC-V

By Brian Bailey - 28 Oct, 2021 - Comments: 2

High-quality RISC-V implementations are becoming more numerous, but it is the extensibility of the architecture that is driving a lot of design activity. The challenge is designing and implementing custom processors without having to re-implement them every time at the register transfer level (RTL). There are two types of high-level synthesis (HLS) that need to be considered. The first is ge... » read more

Hierarchical Verification for EC-FPGA Flow

By OneSpin Solutions - 27 Oct, 2021 - Comments: 0

This document describes the methodology to apply EC-FPGA verification using hierarchical netlists. This approach is recommended in case the verification of the overall design has issues with convergence. The document contains a step-by-step description of different methods while providing reasoning for the soundness of each approach. It is assumed for this document that the reader is familiar w... » read more

The Road To Osmosis

By Rob van Blommestein - 27 Oct, 2021 - Comments: 0

It’s happening. Some may have speculated that, with the acquisition of OneSpin by Siemens, the OneSpin user group meeting, more commonly known as Osmosis, would be formally (pun intended) absorbed into a larger Siemens event. Well, I’m here to tell you that Osmosis is officially on the books and will continue to focus on the specific area of formal verification. The team has been working di... » read more

Security Risks Grow With 5G

By John Koon - 07 Oct, 2021 - Comments: 0

5G mobile phones can download a movie in seconds rather than minutes, but whether that can be done securely remains to be seen. What is clear from technology providers, though, is they are taking security very seriously with this new wireless technology. More data is in motion, and the value of that data is growing as users rely on mobile devices for everything from banking to automotive saf... » read more

Easing The Burden Of Early Bug Detection

By Rob van Blommestein - 26 Aug, 2021 - Comments: 0

Integrated circuit designers are under constant pressure to deliver bug free code that meets ever more rigorous requirements. It is well known that the more bugs that can be detected early in the development process, the faster and easier that development effort will be. However, early bug detection requires a verification overhead on the designer that can be onerous and impact the design proce... » read more

Always On, Always At Risk

By Ed Sperling - 18 Aug, 2021 - Comments: 0

Always-on devices are everywhere, and each of them is a potential target for hackers. While many people associate always-on devices with smart speakers such as an Amazon Alexa or Google Home, or a connected security camera, that's only one component in a system. There's a broader infrastructure behind those devices. So even if you power down a digital assistant/smart speaker, everything it's... » read more

Beyond Bug Hunting: Verification Coverage From Safety To Certification

By OneSpin Solutions - 04 Aug, 2021 - Comments: 0

Understanding verification coverage is critical for meeting IC integrity standards and goes well beyond detecting bugs in the design. Without proper verification coverage metrics, meeting strict safety standards and certification may not be achievable. Precise metrics indicate where there are gaps in verification and provide a clear view of the progress being made in the verification effort. Co... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?