Week In Review: System-Level Design

By Ed Sperling - 07 Feb, 2014 - Comments: 0

Cadence agreed to buy Forte Design Systems for an undisclosed sum, adding further proof that the market for high-level synthesis and tools that run at higher levels of abstraction is finally hitting its stride. Behind this acquisition is a rising pain level due to increasing complexity in SoCs—IP integration, low power concerns and much more of everything, from transistors to memories—has f... » read more

Modern IC Packaging

By Various Writers - 18 Dec, 2013 - Comments: 0

Modern IC packaging technologies, such as 3D-IC, drive the need for IC, package and system co-design tools and methodologies. To download this white paper, click here. » read more

System Bits: Dec. 10

By Brian Bailey - 10 Dec, 2013 - Comments: 0

Lasers From Nano Wires A few weeks ago, Semiconductor Engineering published a special report about silicon photonics and concentrated on the integration of the laser onto the silicon surface. Growing III-V materials on silicon is problematic because of the lattice mismatch, but researchers at the Technische Universität München (TUM) may have found a way around that problem. Thread-like semic... » read more

Tech Talk: 2.5D Stacked Die

By Ed Sperling - 20 Nov, 2013 - Comments: 0

What's the motivation for moving to 2.5D packaging and architectures rather than following Moore's Law? Shafy Eltoukhy, VP of operations and technology development at Open-Silicon, talks with Semiconductor Engineering about adding another dimension in semiconductors. [youtube vid=HwpY9bUNt0w] » read more

Front End Comes To The Back End

By Jeff Chappell - 19 Sep, 2013 - Comments: 0

By Jeff Chappell For outsourced assembly and test (OSAT) houses either planning for or already offering through-silicon via (TSV) capability for their 3D packaging efforts, this has meant the front end is coming to the back end, in a manner of speaking. A bit of an exaggeration perhaps, as most generalizations are. But thanks to TSVs, in a very real sense some of what would typically be the... » read more

3D IC Supply Chain: Still Under Construction

By Barbara Jorgensen - 25 Jul, 2013 - Comments: 1

By Barbara Jorgensen and Ed Sperling Stacked die, which promise high levels of integration, a tiny footprint, energy conservation and blinding speed, still have some big hurdles to overcome. Cost, packaging and manufacturability continue to make steady progress, with test chips being produced by all of the major foundries. But in a disaggregated ecosystem, the supply chain remains a big st... » read more

Foundry Talk

By Ed Sperling - 07 Jul, 2013 - Comments: 0

GlobalFoundries CEO Ajit Manocha sounds off on Foundry 2.0, 450mm wafers, lithography challenges, stacked die, the Internet of Things and the rush to the next process node. [youtube vid=WfjtlZkCi0w] » read more

Inside The Package

By Mark LaPedus - 24 Jan, 2013 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss IC packaging trends with Rich Rice, senior vice president for North America at Taiwan’s Advanced Semiconductor Engineering (ASE), the world’s largest independent IC packaging and test house. SMD: Amazingly, there are still more than 100 vendors competing in the IC test and assembly business today. But for year... » read more

Materials Market To Top $50 Billion In 2013

By Lara Chamness - 20 Sep, 2012 - Comments: 0

By Lara Chamness Given current macroeconomic headwinds, this year is proving to be challenging to forecast. Most analysts recently downgraded their semiconductor revenue forecasts to flat or low-single digits, down from the more optimistic forecasts of 4% to 6% growth presented earlier in the year. SEMI believes that the semiconductor materials will trend with the device market. As such, th... » read more

Packaging Tradeoffs More Complex Than Ever

By Ed Sperling - 24 May, 2012 - Comments: 0

By Ann Steffora Mutschler Driven by high-speed interfaces, the demand for TSVs and the complexities that new process nodes bring, older packaging technologies like wirebonding can’t keep up. The latest and greatest flip chip technologies offer much more flexibility, but at a cost. As such, the package plays a larger role than ever in determining system specifications because, depending o... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: packaging