tag: parasitics

Modeling High-Performance Analog And RF Circuits In Nanometer-Scale CMOS
By Mentor, a Siemens Business - 12 Mar, 2015 - Comments: 0

By Mick Tegethoff and David Lee Today’s consumer, communication, and computer electronic devices have clocks, communication interfaces, and high-speed signal-conditioning circuits that operate at radio frequencies (RF). Providing price-competitive products often requires monolithic integration of these circuits in low-power nanometer-scale bulk CMOS silicon. This is a worst-case scenario for... » read more

One-On-One: Aaron Thean
By Mark LaPedus - 22 Jan, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss process technology, transistor trends and other topics with Aaron Thean, vice president of process technologies and director of the logic devices R&D program at Imec. SE: Chipmakers are ramping up the 16nm/14nm logic node, with 10nm and 7nm in R&D. What’s the current timeline for 10nm and 7nm? Thean: 10nm is on its way. We will see r... » read more

Tech Talk: Photonics, Take 2
By Ed Sperling - 23 Jun, 2014 - Comments: 0

Mentor Graphics’ John Ferguson explains why light is getting so much attention for inter-chip communications, where it excels, and why it has limitations. This is the second part in a two-part series. [youtube vid=4-5FbxIpIk4] To view part 1, click here. » read more

Analog IP Migration Using Design Knowledge Extraction
By Various Writers - 07 Nov, 2013 - Comments: 0

Demonstrated in this paper is a technique for automatic circuit resizing between different technologies. It relies on design knowledge extraction, which renders it very fast compared to full optimization approaches and allows handling of much larger circuits. This technique studies the original design and extracts its major features (basic devices & blocks features, device matching, parasitics,... » read more

Experts At The Table: The Growing Signoff Headache
By Ed Sperling - 07 Jun, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss signoff issues with Rob Aitken, an ARM fellow; Sumbal Rafiq, director of engineering at Applied Micro; Ruben Molina, product marketing director for timing signoff at Cadence; Carey Robertson, director of product marketing for Calibre extraction at Mentor Graphics; and Robert Hoogenstryd, director of marketing for design ... » read more

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