tag: PCI Express

PCI Express Test Overview
By Keysight - 10 Apr, 2024 - Comments: 0

PCl Express, short for Peripheral Component Interconnect Express, is a high-performance and high-bandwidth serial communication interconnect standard. First proposed by Intel and further developed by the Peripheral Component Interconnect Special Interest Group (PCI-SIG) in replacement of bus-based communication architecture, such as PCI, PCI Extended (PCI-X), and Accelerated Graphics Port (AGP)... » read more

New Age Solution For Data Integrity And Authenticity
By Om Prakash - 27 Jun, 2023 - Comments: 0

With the advent of faster processing chips, the rate of data transfer has increased enormously. Be it artificial intelligence (AI), the Internet of Things (IOT), compute intensive analytics, or cloud computing, the demand for processing data in a fraction of a second is huge. Chips with superfast computing capabilities are used in applications where malfunctions can be life threatening, such as... » read more

How The Doubling Of Interconnect Bandwidth With PCI Express 6.0 Impacts IP Electrical Validation
By Synopsys - 09 May, 2023 - Comments: 0

As a result of the innovations taking place in CPUs, GPUs, accelerators, and switches, the interface in hyperscale datacenters now requires faster data transfers both between compute and memory and onto the network. PCI Express (PCIe) provides the backbone for these interconnects and is used to build protocols such as Computer Express Link (CXL) and Universal Chiplet Interconnect Express (UCIe... » read more

PCIe 6.0 Electrical Testing For High Data-Bandwidth Applications
By Cadence - 22 Mar, 2023 - Comments: 0

For nearly three decades, PCI Express (PCIe) technology has been the standard interconnect inside computers providing high bandwidth and low latency to meet customer demand. However, as the industry needs to evolve, so does the standard, keeping pace and driving future innovation. PCIe 6.0 is ubiquitous and offers power-efficient performance and high bandwidth for latency-sensitive applicati... » read more

Leveraging Multi-Protocol PHY For PCIe To Cope With SoC Design Complexity
By Cadence - 26 Jan, 2022 - Comments: 0

Now in the post-Moore’s Law era, the fast-evolving semiconductor market is continually geared toward higher performance and feature-rich integrated chip (IC) solutions. More functional design blocks integrated with growing interconnections—to not only increase the overall throughput but also expand the I/O connectivity—resulted in a more powerful system on chip (SoC). This increasing comp... » read more

Accelerate Adoption Of High-Speed, Low-Latency, Cache-Coherent Standards Using Formal Verification
By Cadence - 09 Jun, 2021 - Comments: 0

We continue to see huge growth in data and compute demand, fueled by increased global data traffic with the 5G rollout, the prevalence of streaming services, and expanded artificial intelligence and machine learning (AI/ML) applications. Several new industry-standard specifications have emerged in recent years to define the protocols of the underlying electronic components and IP building block... » read more

Data Center Evolution: Accelerating Computing With PCI Express 5.0
By Rambus - 09 Jun, 2021 - Comments: 0

The PCI Express (PCIe) interface is the critical backbone that moves data at high bandwidth between various compute nodes such as CPUs, GPUs, FPGAs, and workload-specific accelerators. The rise of cloud-based computing and hyperscale data centers, along with high-bandwidth applications like artificial intelligence (AI) and machine learning (ML), have pushed PCIe 4 to its limits. In this white p... » read more

Connecting Emulated Designs To Real PCIe Devices
By Krzysztof Szczur - 28 May, 2020 - Comments: 0

These days verification teams no longer question whether hardware assisted verification should be used in their projects. Rather, they ask at which stage they should start using it. Contemporary System-on-Chip (SoC) designs are already sufficiently complex to make HDL simulation a bottleneck during verification, without even mentioning hardware-software co-verification or firmware and softwa... » read more

PCIe 5.0 Drill-Down
By Ed Sperling - 01 Apr, 2020 - Comments: 0

Suresh Andani, senior director of product marketing for SerDes IP at Rambus, digs into the new PCI Express standard, why it’s so important for data centers, how it compares with previous versions of the standard, and how it will fit into existing and non-von Neumann architectures. » read more

PCI Express 5 vs. 4: What’s New?
By Rambus - 12 Feb, 2020 - Comments: 0

What’s new about PCI Express 5 (PCIe 5)? The latest PCI Express standard, PCIe 5, represents a doubling of speed over the PCIe 4.0 specifications. We’re talking about 32 Gigatransfers per second (GT/s) vs. 16GT/s, with an aggregate x16 link bandwidth of almost 128 Gigabytes per second (GBps). This speed boost is needed to support a new generation of artificial intelligence (AI) and ma... » read more

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