tag: PCIe 4.0

PCIe 5.0 Drill-Down
By Ed Sperling - 01 Apr, 2020 - Comments: 0

Suresh Andani, senior director of product marketing for SerDes IP at Rambus, digs into the new PCI Express standard, why it’s so important for data centers, how it compares with previous versions of the standard, and how it will fit into existing and non-von Neumann architectures. » read more

PCI Express 5 vs. 4: What’s New?
By Rambus - 12 Feb, 2020 - Comments: 0

What’s new about PCI Express 5 (PCIe 5)? The latest PCI Express standard, PCIe 5, represents a doubling of speed over the PCIe 4.0 specifications. We’re talking about 32 Gigatransfers per second (GT/s) vs. 16GT/s, with an aggregate x16 link bandwidth of almost 128 Gigabytes per second (GBps). This speed boost is needed to support a new generation of artificial intelligence (AI) and ma... » read more

PCIe 4.0 Hangs In, PCIe 5.0 Coming On Strong
By Mondeep Thiara - 17 Jan, 2019 - Comments: 0

First introduced in 2003 as a universal serial chip-to-chip interface running at 2.5 Gbps, PCI Express (Peripheral Component Interconnect Express), also known as PCIe, has advanced several revisions with significant improvements to performance and other features with each new generation. Through broad support, backwards compatibility, and a consistent cadence of upgrades that doubled lane sp... » read more

The Week In Review: Design
By Jesse Allen - 27 Apr, 2018 - Comments: 0

M&A Alibaba acquired C-Sky Microsystems, which focuses on 32-bit embedded CPU IP cores in both low power and high performance varieties, as well as SoC and MCU platforms. Founded in 2001, the Hangzhou, China-based C-Sky previously received investment from Alibaba, and the two companies collaborated on a hardware and software platform for IoT and cloud integration. The deal comes on the hee... » read more

Blog Review: Feb. 7
By Jesse Allen - 07 Feb, 2018 - Comments: 0

Cadence's Paul McLellan checks out why DARPA's excited about open-source IP at last year's RISC-V conference. Synopsys' Richard Solomon checks out what's new in PCIe 4.0, from the 16GT/s data rate to lane margining. Mentor's Colin Walls shares another set of tips for embedded software developers, including when to use [ ] and exception handling. Arm's Jason Andrews presents a tutorial ... » read more

Optimizing The Data Center With PCI Express 4.0
By Niraj Mathur - 14 Dec, 2017 - Comments: 1

PCI Express (Peripheral Component Interconnect Express), also known as PCIe, is a high-speed serial computer expansion bus standard designed to replace older PCI, PCI-X and AGP bus standards. Officially launched in 2003, PCIe was rapidly adopted by chip, system and software designers and emerged as the dominant interface standard for connecting peripherals to the CPU. Modern CPUs rely on the... » read more

The Week In Review: Design
By Jesse Allen - 27 Oct, 2017 - Comments: 0

M&A PLDA is divesting its Reflex CES brand. The FPGA board maker will become wholly managed by its own management and investment teams. In 2015, Reflex CES took over the hardware businesses of PLDA, including FPGA-based boards and the System-on-Module product lines. Tools Mentor uncorked a new tool for in-system test and diagnosis of automotive ICs. Tessent MissionMode provides infrast... » read more

The Week In Review: Design
By Jesse Allen - 09 Jun, 2017 - Comments: 1

Tools Mentor added new tools to its high-level synthesis portfolio. The DesignChecks tool helps find bugs during coding with a static mode that performs very fast linting-like checks of the code and a formal mode that uses a formal engine for a more exhaustive proof of issues. The synthesis-aware Coverage tool measures code coverage for C++ signoff and fast closure of synthesized RTL. It sup... » read more

PCI Express 4.0 Controller Design And Integration Challenges
By Synopsys - 08 Jul, 2015 - Comments: 0

Designers need to start planning for PCI Express 4.0 integration now, because decisions for the PCIe 4.0 controller can have far-reaching consequences for the entire SoC. This paper describes the market adoption and expected use of PCIe 4.0; covers the specification; and discusses three challenges the new specification brings to controller designers. Outline Markets & Applications fo... » read more

The Week In Review: Design
By Ed Sperling - 16 May, 2014 - Comments: 0

M&A Synopsys’ Coverity subsidiary bought Kalistick, a French company that makes cloud-based solutions to boost testing efficiency by allowing engineers to identify and prioritize tests. Terms of the deal were not disclosed. Tools Cadence rolled out verification IP for the new PCI Express 4.0 architecture. The new spec supports up to 16 billion transactions per second, which is double... » read more

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