The Week In Review: Design

Coverity buys cloud company; Cadence adds PCIe 4 VIP; Mentor unveils industrial tester; Cadence IP qualified for FD-SOI; Rambus joins JEDEC group; Si2 rolls out OA polygon extensions standard.


SynopsysCoverity subsidiary bought Kalistick, a French company that makes cloud-based solutions to boost testing efficiency by allowing engineers to identify and prioritize tests. Terms of the deal were not disclosed.

Cadence rolled out verification IP for the new PCI Express 4.0 architecture. The new spec supports up to 16 billion transactions per second, which is double the speed of PCIe 3.0.

Mentor Graphics uncorked an industrial power tester for power cycling and thermal testing of electronics components to simulate and measure lifetime performance. The tester is targeted for industries such as automotive and transportation, power generators and wind turbines.

Cadence joined the Samsung-STMicroelectronics-Soitec party for 28nm FD-SOI, announcing availability of a variety of qualified IP, including DDR4 and high-speed inter-chip PHY IP. The company also said its digital implementation, signoff and custom/analog tools are qualified for the FD-SOI process.

Cadence also won a deal with HiSilicon, which is adding more emulation platforms for its mobile and digital media chip development.

Rambus joined the JEDEC committee to define advanced server memory systems. The goal is to create faster, cheaper, and lower power memory.

Certifications & Standards
Mentor Graphics’ Analog FastSPICE platform was certified for TSMC’s SPICE v. 1.0 spec.

Si2 released its OpenAccess Polygon Operators Extension, which allows for manipulation of OpenAccess objects using Boolean operations, interacting selections and other functions involving detection and manipulation of physical design patterns.

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