tag: PCIe 5.0

Accelerating Simulation Of PCIe Controllers For DMA Applications
By Akshay Sarup - 10 Sep, 2020 - Comments: 0

For memory-intensive and high-performance computing, direct memory access (DMA) is indispensable. A typical DMA operation in PCI Express (PCIe) entails the transfer of data from the system memory to end point devices using a point-to-point PCIe bus to reduce latency and increase memory access throughput between the CPU and the device. Verification of DMA engines is concentrated on the data t... » read more

PCIe 5.0 Drill-Down
By Ed Sperling - 01 Apr, 2020 - Comments: 0

Suresh Andani, senior director of product marketing for SerDes IP at Rambus, digs into the new PCI Express standard, why it’s so important for data centers, how it compares with previous versions of the standard, and how it will fit into existing and non-von Neumann architectures. » read more

PCI Express 5 vs. 4: What’s New?
By Rambus - 12 Feb, 2020 - Comments: 0

What’s new about PCI Express 5 (PCIe 5)? The latest PCI Express standard, PCIe 5, represents a doubling of speed over the PCIe 4.0 specifications. We’re talking about 32 Gigatransfers per second (GT/s) vs. 16GT/s, with an aggregate x16 link bandwidth of almost 128 Gigabytes per second (GBps). This speed boost is needed to support a new generation of artificial intelligence (AI) and ma... » read more

The New CXL Standard
By Ed Sperling - 16 Sep, 2019 - Comments: 0

Gary Ruggles, senior staff product marketing manager at Synopsys, digs into the new Compute Express Link standard, why it’s important for high bandwidth in AI/ML applications, where it came from, and how to apply it in current and future designs. » read more

Week In Review: Design, Low Power
By Jesse Allen - 31 May, 2019 - Comments: 0

M&A NXP will acquire Marvell's Wi-Fi Connectivity business in an all-cash, asset transaction valued at $1.76 billion. The deal includes the Wi-Fi and Bluetooth technology portfolios and related assets; the business employs approximately 550 people worldwide. The deal is expected to close by calendar Q1 2020. Tools Cadence unveiled a data center-optimized FPGA-based prototyping system, ... » read more

Getting Ready for 32 GT/s PCIe 5.0 Designs
By Gary Ruggles - 14 Feb, 2019 - Comments: 1

The transition from older PCI Express (PCIe) technologies to the latest Revision 5.0 is on an accelerated path, with system-on-chip (SoC) designers seeing a much faster roll out than they did with PCIe 4.0. The recent release of version 0.9 of the PCIe 5.0 Base Specification locks in the functional changes to the specification, allowing designers to confidently start their designs. With the rap... » read more

PCIe 4.0 Hangs In, PCIe 5.0 Coming On Strong
By Mondeep Thiara - 17 Jan, 2019 - Comments: 0

First introduced in 2003 as a universal serial chip-to-chip interface running at 2.5 Gbps, PCI Express (Peripheral Component Interconnect Express), also known as PCIe, has advanced several revisions with significant improvements to performance and other features with each new generation. Through broad support, backwards compatibility, and a consistent cadence of upgrades that doubled lane sp... » read more

The Week In Review: Design
By Jesse Allen - 08 Jun, 2018 - Comments: 0

Tools & IP Synopsys added machine learning capabilities to its Design Platform. The company highlighted benefits to the PrimeTime signoff tool, which saw 5X faster power recovery in customer designs at leading-edge geometries. Renesas is using the tool, noting a 4X power ECO speed-up. ArterisIP unveiled a standalone last level cache (LLC) for high-performance SoCs. CodaCache can be adde... » read more

32GT/s PCI Express Design Considerations
By Rita Horner - 08 Mar, 2018 - Comments: 0

Today’s networking and rapidly emerging artificial intelligence (AI) applications are requiring more bandwidth in accelerators and GPUs, as well as faster interconnects to transmit and receive greater amounts of data. Towards the middle of 2017 the PCI-SIG industry consortium announced its latest specification, PCIe 5.0, which raised the data rate from 16GT/s to 32GT/s and doubled the link... » read more

The Week In Review: Design
By Jesse Allen - 01 Dec, 2017 - Comments: 0

Tools Imperas debuted its RISC-V Processor Developer Suite, a set of models, a software simulator, and tools to validate, verify, and provide early estimation of timing performance and power consumption for RISC-V processors. IP Minima Processor revealed its dynamic-margining subsystem IP for near-threshold voltage design. The startup's hardware and software IP works with a CPU or DSP proc... » read more

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