tag: physical verification

The Week In Review: Design
By Jesse Allen - 22 Jun, 2018 - Comments: 0

Tools Synopsys revealed a power analysis solution for early SoC design as well as signoff-accurate power and reliability closure. PrimePower has reliability as a major focus, expanding power and reliability signoff and ECO closure capabilities from physical awareness to cell electromigration effects. Supported power types include peak power, average power, clock network power, leakage power, a... » read more

Calibre Evolves Constantly
By Mike Santarini - 11 May, 2017 - Comments: 0

I find it truly amazing that despite the constantly changing tide in the digital IC design industry that some tools have remained in that number 1 spot for over a decade. The three tools that immediately come to mind are Synopsys’ PrimeTime and Design Compiler and Mentor’s Calibre. I remember back when I first started covering the industry in the mid-1990s that Quad Design’s Motive sta... » read more

FinFET And Multi-Patterning Aware Place-And-Route Implementation
By Mentor, a Siemens Business - 18 Jan, 2017 - Comments: 0

The use of finFETs and multi-patterning has a huge impact on the entire physical implementation flow. This paper outlines the new challenges in placement, routing, optimization, and physical verification and describes how the Nitro-SoC place and route system handles them. To read more, click here. » read more

Using Automated Pattern Matching For SRAM Physical Verification
By Elven Huang - 15 Dec, 2016 - Comments: 0

How often have you struggled to verify static random-access memory (SRAM) blocks in your design? And how often, no matter how much time you spend on them, do they end up causing manufacturing issues? Memory is a critical component in today’s SoC designs, often consuming 50% or more of the die area. SRAM blocks are typically assembled in a layout using a set of specific intellectual propert... » read more

One Flow To Rule Them All
By Brian Bailey - 12 Nov, 2015 - Comments: 0

The new mantra of shift left within EDA is nothing new and first made an appearance more than a decade ago. At that time there was a very large divide between logic synthesis and place and route. As wire delays became more important, timing closure became increasingly difficult with a logic synthesis flow that did not take that into account. The tools subsequently became tied much closer togeth... » read more

Ensuring Optimal Performance For Physical Verification
By Mentor, a Siemens Business - 22 Jul, 2015 - Comments: 0

By accessing the most recently qualified version of foundry rule files, users get the most efficient rule implementations. By adopting the most recent version of Calibre, users get the latest improvements in available operations, operation performance, data hierarchy optimization and total scaling, providing the best possible performance and minimizing runtimes. Design teams running full-chip D... » read more

Incremental Design Methodologies
By Brian Bailey - 26 Feb, 2015 - Comments: 0

There are times when we become stuck in the past, or choose to believe something that is no longer true or actually never was true. As we get older, we are all guilty of that. History tends to rewrite itself, especially given that this industry is aging. One of these situations occurred recently, and comments from an industry luminary didn’t align with the thoughts and memories of other peopl... » read more

The Route To Faster Physical Verification And Better Designs
By Jean-Marie Brunet - 18 Sep, 2014 - Comments: 0

By Nancy Nguyen & Jean-Marie Brunet As we’ve moved to today’s leading-edge nodes, physical layout designers have faced more and more challenges to get their design to tape-out on schedule. Timing becomes increasingly difficult to converge, power reduction for both IR and leakage becomes a big issue, and most importantly, how do we meet all of the ever-growing and more complex signoff d... » read more

Signoff Intensity On The Rise
By The SE Staff - 15 Aug, 2014 - Comments: 2

By Ann Steffora Mutschler and Ed Sperling Lithography and signoff are crossing swords at 16/14nm and 10nm, creating new problems that raise questions about just how confident design teams will be when they sign off before tapeout — and how many respins are likely to follow. While designs at 20nm, 16nm and 14nm typically rely on colorless double patterning, at 10nm colors are mandatory. ... » read more

Reducing IC Cycle Time With Calibre
By Various Writers - 15 Nov, 2012 - Comments: 0

Technology is both a blessing and a curse. The same shrinking of transistor size that has enabled chip designers to place significantly more functionality on the same die area is also responsible for the significant increases we have seen in the number and complexity of verification rules. It would be nice if we could use this phenomenon to our advantage, as an excuse for why our job of physica... » read more

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