tag: physical verification

Signoff-Accurate Partial Layout Extraction And Early Simulation
By Soni Kapoor - 11 Aug, 2022 - Comments: 0

It is a rewarding experience for EDA developers and users to collaborate on deploying advanced techniques to improve design productivity. This blog will describe the experience of collaborating with customers on a new technology for reducing the number of analog design iterations. Analog design requires that engineers balance the needs to 1) reach market quickly 2) deliver high quality 3) at lo... » read more

2.5/3D IC Reliability Verification Has Come A Long Way
By Dina Medhat - 01 Aug, 2022 - Comments: 0

2.5D/3D integrated circuits (ICs) have evolved into an innovative solution for many IC design and integration challenges. As shown in figure 1, 2.5D ICs have multiple dies placed side-by-side on a passive silicon interposer. The interposer is placed on a ball grid array (BGA) organic substrate. Micro-bumps attach each die to the interposer, and flip-chip (C4) bumps attach the interposer to the ... » read more

Cutting Clock Costs On The Bleeding Edge Of Process Nodes
By Aakash Jani - 01 Aug, 2022 - Comments: 0

In a recent study done by McKinsey and IDC, we see that physical design and verification costs are increasing exponentially with shrinking transistor sizes. As figure 1 shows, physical design (PD) and pre-silicon verification costs are doubling each process leap. As companies leap from node to leading node, a natural question arises. Why is it becoming harder and more expensive to tapeout a chi... » read more

High-Performance 5G IC Designs Need High-Performance Parasitic Extraction
By Karen Chow - 23 Jun, 2022 - Comments: 0

By Karen Chow and Salma Ahmed Elhenedy We are rapidly approaching a future where 5G telecommunications will be the norm. With its increased data speeds and bandwidth, 5G has the potential to change the way we live our lives. But what does that mean for the average person? Think about cellphones, for one. You don't just use your phone for calling or texting anymore—you surf the web, chec... » read more

Improving PPA With AI
By John Koon - 12 May, 2022 - Comments: 0

AI/ML/DL is starting to show up in EDA tools for a variety of steps in the semiconductor design flow, many of them aimed at improving performance, reducing power, and speeding time to market by catching errors that humans might overlook. It's unlikely that complex SoCs, or heterogeneous integration in advanced packages, ever will be perfect at first silicon. Still, the number of common error... » read more

Dissolving The Barriers In Multi-Substrate 3D-IC Assembly Design
By Tarek Ramadan - 24 Feb, 2022 - Comments: 0

Advanced packaging continues to promise improved form factor, cost, performance, and functionality compared to the traditional transistor scaling on SoCs. This is done by integrating multiple dies on top of a substrate (organic or silicon). Besides multiple dies, multiple substrates can typically exist in a 3D-IC assembly. In this case, the benefits of advanced packaging are taken to a whole ne... » read more

Optimize Physical Verification Cost Of Ownership
By Manoz Palaparthi - 29 Jul, 2021 - Comments: 0

As semiconductor designs continue to grow in size and complexity, they put increasing pressure on every stage of the design process. Physical verification, often on the critical path to tape-out, is especially affected. Design rule checking (DRC), layout versus schematic (LVS), and other physical verification runs take longer as chip size increases. In addition, finer geometries introduce new c... » read more

Early Detection Of Power/Ground Shorts Speeds Time To Tapeout
By Mentor, a Siemens Business - 27 May, 2020 - Comments: 0

Early detection of power/ground shorts lets design teams fix errors during implementation, avoiding time-consuming design data merging and full-chip physical verification. The Calibre platform provides fast, automated power/ground checking using abstract LEF/DEF input, significantly reducing the time and resources needed to ensure these violations are removed prior to tapeout. To read more, ... » read more

Physical Verification For Photonics Integrated Circuits
By Manoz Palaparthi - 26 Mar, 2020 - Comments: 0

Silicon photonics is a promising solution for the explosive growth of data volume and network traffic in computing and communications. Silicon photonics integrates photonics applications on a silicon wafer, utilizing mainstream Si-based technology. Photonics integrated circuits (PIC) offer several advantages over traditional integrated circuits: faster data transfer speeds, lower power consumpt... » read more

Fast-Track Your Early SoC Design Exploration And Verification
By Nermeen Hossam - 26 Sep, 2019 - Comments: 0

By Nermeen Hossam and John Ferguson Most advanced node system-on-chip (SoC) designs are very large, and very complex. They typically contain many blocks and intellectual property (IP) that perform specialized functions, such as computation, internal communications, and signal processing. These blocks are often built by separate teams or IP suppliers, and integrated into the SoC layout. Howev... » read more

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