SoC Integration Headaches Grow


As the number of IP blocks grows, so do the headaches of integrating the various pieces and making sure they perform as planned within a prescribed power envelope. This is easier said than done, particularly at the most advanced process nodes. There are more blocks, more power domains, more states and use-model dependencies, and there is much more contention for memories. There are physical ... » read more

The Old Two-Step Just Doesn’t Have That Swing


Power analysis has quickly become equally as important as functional verification for today's power-hungry SoCs. Yet, until now, it was not possible to fully analyze dynamic power in very large SoCs running embedded software. That day has finally arrived with new emulation platform software that overcomes the intrinsic shortcomings of the current two-step power estimation tools. The current ... » read more

Power Usage Shift Leads To Methodology Shift


Veloce offers a unique and customized flow for SoC power exploration and analysis. Veloce Power Application is enabling a methodology shift in the way power measurements are done to address the new requirements due to usage shift. Chip designers do not need to rely on functional test benches and extrapolation techniques to come up with power number. The new flow enables booting OS, running live... » read more

Package Modeling Needs For A Robust IC Power Integrity Sign-Off


Progress in IC technology has allowed chip designers to pack more functionality and continually make better use of silicon area. This trend, coupled with the need to maintain low power using techniques such as voltage islands and power and clock gating, has caused the power consumption to vary across the chip and over time. This has introduced considerable amount of transient current peaks in t... » read more

Veloce System-Level Power Analysis And Verification


Power analysis and verification need to move to the system level, improving upon and extending the capabilities and scope of RTL and gate-level techniques. The performance, capacity, and flexibility of emulation platforms make them the ideal technology for system-level power analysis and verification. Veloce delivers unprecedented power verification and analysis capabilities. This paper shares ... » read more

Advanced Power And Performance Optimization For Multicore SoCs


The Multicore Optimization (MCO) technology in Synopsys Platform Architect provides an environment for early exploration and optimization of complex Multicore SoC (MP-SoC) platforms. It allows quantitative analysis of performance and power metrics to avoid SoC market failure due to underperforming or power hungry architectures. To read more, click here. » read more

What’s Working For Power Verification


Getting power verification right — or at least good enough — is the source of frustration for many design teams. Add to this the fact that there is no one right way to accomplish it just compounds the challenge. Fortunately, there are a number of options that are working to varying degrees, starting with static verification, according to Bernard Murphy, CTO of Atrenta. “Static verifica... » read more

Tech Talk: Power Optimization II


Solaiman Rahim, senior director of engineering at Atrenta, talks with Semiconductor Engineering about where to put your efforts to reap the greatest rewards in power reduction and optimization. This is the second of two parts. [youtube vid=OWyzIyEH_pQ] Part one can be viewed here. » read more

Tech Talk: Power Optimization


Solaiman Rahim, senior director of engineering at Atrenta, talks with Semiconductor Engineering about where to put your efforts to reap the greatest rewards in power reduction and optimization. [youtube vid=czK60j65JLo] » read more

Extending Power Analysis To The Emulation of Complex SoCs


Using hardware emulation to estimate SoC power consumption delivers significant value. Emulators are capable of long runs on large designs, making it practical to emulate an RTOS boot sequence or graphics processing of multiple frames. Estimating power consumption of these advanced functions executing across the complete SoC provides valuable insight into the chip’s power draw and its impact ... » read more

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