tag: power estimation

The Power Estimation Challenge
By Lauro Rizzatti - 09 Apr, 2015 - Comments: 0

If you wonder how important low power is in chip design today, consider the recent news in the blogosphere reporting the controversy surrounding Qualcomm’s Snapdragon 810 SoC — the company’s first flagship 64-bit chip, which will most likely power the top Android devices released in 2015. The story broke in early December along the lines that the 810 had problems with overheating. Whet... » read more

Unraveling Power Methodologies
By Brian Bailey - 15 Jan, 2015 - Comments: 0

When working on articles, the editors at Semiconductor Engineering sometimes hear things that make them stand back and question what seems to be an industry truth. One such statement happened last month while researching a different article. The statement was: Most designs are not top-down, but in fact bottom-up when it comes to power management. The most used methodology today is that the RTL... » read more

What’s Working For Power Verification
By Ann Mutschler - 07 Nov, 2014 - Comments: 2

Getting power verification right — or at least good enough — is the source of frustration for many design teams. Add to this the fact that there is no one right way to accomplish it just compounds the challenge. Fortunately, there are a number of options that are working to varying degrees, starting with static verification, according to Bernard Murphy, CTO of Atrenta. “Static verifica... » read more

Making Accurate Power Estimates At RTL
By Rob Eccles - 14 Oct, 2014 - Comments: 0

It may seem counterintuitive, but an accurate estimation of power at Register Transfer Level can be made. In this blog, we will learn how it can be done. The main ingredient In order to understand RTL power estimation, let us first consider making the power estimation at gate level. At gate level we have a netlist that contains standard cell instances. These standard cells have been charact... » read more

Can RTL Power Estimation Accuracy Be Improved?
By Mark Baker - 10 Apr, 2014 - Comments: 0

The power targets for today’s complex SoC designs force design teams to address power optimization earlier and more effectively than ever before. In recent years, design teams have migrated to RTL power estimation solutions to identify areas of potential power savings to be used in early design tradeoffs. RTL power estimation accuracy at 15% to 20% to gate-level power numbers is deemed accept... » read more

How to Achieve Estimation, Reduction, And Verification Of Power In RTL Designs
By Various Writers - 15 Jan, 2014 - Comments: 0

Maintaining power dissipation at low levels is a major concern in modern day IC designs. For wireless electronic appliances, battery life is one of the major influencers of the purchase decision and is an effective differentiator. Mobile phones, digital cameras and personal MP3 players are increasingly being sold based on their battery lives. In wired applications, power consumption determines ... » read more

Current Generation Of FPGAs Pose New Power And Reliability Challenges
By Annapoorna Krishnaswamy - 07 Nov, 2013 - Comments: 0

Today’s FPGAs are being used in a wide variety of applications such as consumer electronics, computer and storage, automotive electronics, and mission critical applications. The flexibility to configure the device based on its need, the ability to reprogram its functions, and the hardware parallelism it offers to quickly process very large amounts of data are some of the reasons why off-the-s... » read more

The Week In Review: May 31
By Ed Sperling - 31 May, 2013 - Comments: 0

By Ed Sperling Mentor Graphics and GlobalFoundries teamed up to deliver 20nm design kits that include Mentor’s place and route tool, including verification and conflict resolution engines for double-patterning violations. The 20nm process is used for GlobalFoundries’ 14nm finFETs. Mentor also received 16nm finFET certification from TSMC for the same tools plus its physical verification pl... » read more

Dealing With The Data Glut
By Ann Mutschler - 11 Apr, 2013 - Comments: 0

By Ann Steffora Mutschler Tools like emulation and simulation are an absolute necessity to design and verify today’s complex SoCs, but what happens when you want to do power analysis and the file sizes are too massive for the emulator to handle? Even with an emulator a five-minute mobile phone call could take three months. Understandably, this issue is causing pain to many design teams... » read more

RTL Power Estimation
By Luke Lang - 14 Apr, 2011 - Comments: 0

By Luke Lang A few months ago, I wrote about power estimation—finding the worst-case toggle rate to determine the worst-case power. This has been used very successfully by many designers to get an accurate estimation and analysis of power dissipation. These designers also are using the worst-case toggle rate to optimize power grid and meet dynamic IR drop requirements. With these power estim... » read more

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