tag: process modeling

Improving DRAM Device Performance Through Saddle Fin Process Optimization
By Taeyon (TY) Oh - 15 Jun, 2023 - Comments: 0

As DRAM technology nodes have scaled down, access transistor issues have been highlighted due to weak gate controllability. Saddle Fins with Buried Channel Array Transistors (BCAT) have subsequently been introduced to increase channel length, prevent short channel effects, and increase data retention times [1]. However, at technology nodes beyond 20nm, securing sufficient device performance (su... » read more

The Impact Of Metal Gate Recess Profile On Transistor Resistance And Capacitance
By Pradeep Nanja - 18 May, 2023 - Comments: 0

In logic devices such as finFETs (field-effect transistors), metal gate parasitic capacitance can negatively impact electrical performance. One way to reduce this parasitic capacitance is to optimize the metal gate recess dimensions. However, there are limits to reducing this capacitance if you simply remove more of the metal material, since this can modify capacitance unexpectedly through chan... » read more

A Comparative Evaluation Of DRAM Bit-Line Spacer Integration Schemes
By Dempsey Deng - 16 Mar, 2023 - Comments: 0

With decreasing dynamic random-access memory (DRAM) cell sizes, DRAM process development has become increasingly difficult. Bit-line (BL) sensing margins and refresh times have become problematic as cell sizes have decreased, due to an increase in BL parasitic capacitance (Cb). The main factor impacting Cb is the parasitic capacitance between the BL and the node contact (CBL-NC) [1]. To reduce ... » read more

Facing Off Against Growing Chip Design Complexity
By Kelly Damalou - 19 Dec, 2022 - Comments: 0

The semiconductor industry continues to face incredible pressures to deliver higher levels of performance in a smaller area, with lower power demands. From high-performance systems-on-chip for 5G mobile devices and network infrastructure to the radio-frequency transceivers that enable autonomous vehicles and the industrial Internet of Things, today’s applications demand a reduced profile, pai... » read more

Insights Into Advanced DRAM Capacitor Patterning: Process Window Evaluation Using Virtual Fabrication
By Qingpeng Wang - 20 Oct, 2022 - Comments: 0

With continuous device scaling, process windows have become narrower and narrower due to smaller feature sizes and greater process step variability [1]. A key task during the R&D stage of semiconductor development is to choose a good integration scheme with a relatively large process window. When wafer test data is limited, evaluating the process window for different integration schemes can... » read more

How Does Line Edge Roughness (LER) Affect Semiconductor Performance At Advanced Nodes?
By Yu De Chen - 26 Sep, 2022 - Comments: 0

BEOL metal line RC delay has become a dominant factor that limits chip performance at advanced nodes [1]. Smaller metal line pitches require a narrower line CD and line to line spacing, which introduces higher metal line resistance and line to line capacitance. This is demonstrated in figure 1, which displays a simulation of line resistance vs. line CD across different BEOL metals. Even without... » read more

3D NAND Virtual Process Troubleshooting And Investigation
By Brett Lowe - 18 Aug, 2022 - Comments: 0

Modern semiconductor processes are extremely complicated and involve thousands of interacting individual process steps. During the development of these process steps, roadblocks and barriers are often encountered in the form of unanticipated negative interactions between upstream and downstream process modules. These barriers can create a long delay in the development cycle and increase costs. ... » read more

BEOL Integration For The 1.5nm Node And Beyond
By Assawer Soussou - 25 Apr, 2022 - Comments: 0

As we approach the 1.5nm node and beyond, new BEOL device integration challenges will be presented. These challenges include the need for smaller metal pitches, along with support for new process flows. Process modifications to improve RC performance, reduce edge placement error, and enable challenging manufacturing processes will all be required. To address these challenges, we investigated th... » read more

Accelerating Semiconductor Process Development Using Virtual Design Of Experiments
By Qingpeng Wang - 17 Mar, 2022 - Comments: 0

Design of Experiments (DOE) are a powerful concept in semiconductor engineering research and development. DOEs are sets of experiments used to explore the sensitivity of experimental variables and their effect on final device performance. A well-designed DOE can help an engineer achieve a targeted semiconductor device performance using a limited number of experimental wafer runs. However, in se... » read more

The Effect Of Pattern Loading On BEOL Yield And Reliability During Chemical Mechanical Planarization
By Taeyon (TY) Oh - 20 Jan, 2022 - Comments: 0

Chemical mechanical planarization (CMP) is required during semiconductor processing of many memory and logic devices. CMP is used to create planar surfaces and achieve uniform layer thickness during semiconductor manufacturing, and to optimize the device topology prior to the next processing step. Unfortunately, the surface of a semiconductor device is not uniform after CMP, due to different re... » read more

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