tag: PTB

Buried Si/SiGe Interfaces Investigated Using Soft X-Ray Reflectometry and STEM-EDX
By Technical Paper Link - 27 Aug, 2024 - Comments: 0

A new technical paper titled "Interface sharpness in stacked thin film structures: a comparison of soft X-ray reflectometry and transmission electron microscopy" was published by researchers at Physikalisch-Technische Bundesanstalt (PTB), imec, and Thermo Fisher Scientific Inc. The paper states: "A key element of semiconductor fabrication is the precise deposition of thin films. Among other... » read more

High-NA EUV May Be Closer Than It Appears
By Katherine Derbyshire - 16 Jun, 2022 - Comments: 1

High-NA EUV is on track to enable scaling down to the Angstrom level, setting the stage for chips with even higher transistor counts and a whole new wave of tools, materials, and system architectures. At the recent SPIE Advanced Lithography conference, Mark Phillips, director of lithography hardware and solutions at Intel, reiterated the company’s intention to deploy the technology in high... » read more

Photomask Challenges At 3nm And Beyond
By Mark LaPedus - 25 Jan, 2022 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss optical and EUV photomasks issues, as well as the challenges facing the mask business, with Naoya Hayashi, research fellow at DNP; Peter Buck, director of MPC & mask defect management at Siemens Digital Industries Software; Bryan Kasprowicz, senior director of technical strategy at Hoya; and Aki Fujimura, CEO of D2S. What f... » read more

Why Mask Blanks Are Critical
By Mark LaPedus - 21 Oct, 2021 - Comments: 1

Geoff Akiki, president of Hoya LSI at the Hoya Group, sat down with Semiconductor Engineering to talk about optical and extreme ultraviolet (EUV) lithography as well as mask blanks. What follows are excerpts of that discussion. SE: Mask blanks are components that serve as the base or the substrate for a photomask. Why are they critical? Akiki: If you look at Hoya, we've been positioned as... » read more

EUV Challenges And Unknowns At 3nm and Below
By Mark LaPedus - 19 Nov, 2020 - Comments: 1

The chip industry is preparing for the next phase of extreme ultraviolet (EUV) lithography at 3nm and beyond, but the challenges and unknowns continue to pile up. In R&D, vendors are working on an assortment of new EUV technologies, such as scanners, resists, and masks. These will be necessary to reach future process nodes, but they are more complex and expensive than the current EUV pro... » read more

Next EUV Issue: Mask 3D Effects
By Mark LaPedus - 25 Apr, 2018 - Comments: 6

As extreme ultraviolet (EUV) lithography moves closer to production, the industry is paying more attention to a problematic phenomenon called mask 3D effects. Mask 3D effects involve the photomask for EUV. In simple terms, a chipmaker designs an IC, which is translated from a file format into a photomask. The mask is a master template for a given IC design. It is placed in a lithography scan... » read more

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