High Performance, Multi-Chip Leadframe Package With Internal Connections

By DaeYoung Park - 19 Dec, 2023 - Comments: 0

For high performance applications, demand for highly integrated packages has increased. This is due to the highly integrated package’s electrical performance advantages of reduction of interchip distance (delay), high density I/O counts for multi-function and small form factor [1-3]. With the increasing importance of highly integrated packages, the need for improved thermal management is also... » read more

Enhancing Punch MLF Packaging with Edge Protection Technology

By Amkor - 14 Jun, 2023 - Comments: 0

Quad Flat No-Lead (QFN) semiconductor packaging provides a small form factor as well as good electrical and thermal performance for low cost. Add demonstrated long term reliability to its benefits and it is easy to see why it has been a preferred automotive package for many years. QFNs are offered in saw and punch formats with punch being a well-defined and used solution in the automotive marke... » read more

Meeting Cost And Technology Requirements Using MLF/QFN

By Amkor - 14 Dec, 2022 - Comments: 0

MicroLeadFrame (MLF)/ quad flat no-lead (QFN) packaging technology is the fastest growing IC packaging solution today. From a market segment perspective, MLF packaging solutions represent more than a 111B-unit market for 2022 across five markets: automotive, consumer, industrial, networking, and communications (Figure 1). The package solution requirements across these markets vary but, the fund... » read more

Packaging Solutions For Unique Markets

By Marc Mangrum - 16 Jun, 2022 - Comments: 0

The MicroLeadframe (MLF/QFN) packaging technology is the fastest growing IC packaging solution today. From a market segment perspective, MLF packaging solutions represent a >111B-unit market for 2022 across 5 unique markets: automotive, consumer, industrial, computing/networking, and communications. The package solution requirements across these markets varies but, the fundamental values the... » read more

Conceptualized Improvement on Transparent Glass Die for a Robust Manufacturing Process

By Technical Paper Link - 17 Jan, 2022 - Comments: 0

Abstract: "Glass die are one of the materials used by semiconductor plants during production of specialized quad-flat no-leads (QFN) products. With its transparent appearance and fragile characteristics, several challenges are encountered and analyzed to resolve unwanted issues and to have a robust process manufacturing. This paper will discuss a potential concept of process improvement on t... » read more

System-In-Package Thrives In The Shadows

By Mark LaPedus - 16 Sep, 2021 - Comments: 0

IC packaging continues to play a big role in the development of new electronic products, particularly with system-in-package (SiP), a successful approach that continues to gain momentum — but mostly under the radar because it adds a competitive edge. With a SiP, several chips and other components are integrated into a package, enabling it to function as an electronic system or sub-system. ... » read more

Challenges With Chiplets And Packaging

By Mark LaPedus - 15 Sep, 2021 - Comments: 0

Semiconductor Engineering sat down to discuss IC packaging technology trends, chiplets, shortages and other topics with William Chen, a fellow at ASE; Michael Kelly, vice president of advanced packaging development and integration at Amkor; Richard Otte, president and CEO of Promex, the parent company of QP Technologies; Michael Liu, senior director of global technical marketing at JCET; and Th... » read more

Fan-Out Packaging Options Grow

By Mark LaPedus - 17 Jun, 2021 - Comments: 0

Chipmakers, OSATs and R&D organizations are developing the next wave of fan-out packages for a range of applications, but sorting out the new options and finding the right solution is proving to be a challenge. Fan-out is a way to assemble one or more dies in an advanced package, enabling chips with better performance and more I/Os for applications like computing, IoT, networking and sma... » read more

Making Chip Packaging More Reliable

By Mark LaPedus - 15 Apr, 2021 - Comments: 0

Packaging houses are readying the next wave of IC packages, but these products must prove to be reliable before they are incorporated into systems. These packages involve several advanced technologies, such as 2.5D/3D, chiplets and fan-out, but vendors also are working on new versions of more mature package types, like wirebond and leadframe technologies. As with previous products, packaging... » read more

Shortages, Challenges Engulf Packaging Supply Chain

By Mark LaPedus - 18 Feb, 2021 - Comments: 0

A surge in demand for chips is impacting the IC packaging supply chain, causing shortages of select manufacturing capacity, various package types, key components, and equipment. Spot shortages in packaging surfaced in late 2020 and have since spread to other sectors. There are now a variety of choke points in the supply chain. Wirebond and flip-chip capacity will remain tight throughout 2021... » read more

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Knowledge Centers
Entities, people and technologies explored

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by Brian Bailey

Partitioning In The Chiplet Era

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by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

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Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

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by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?