Variation Making Trouble In Advanced Packages


Variation is becoming increasingly problematic as chip designs become more heterogeneous and targeted by application, making it difficult to identify the root cause of problems or predict what can go wrong and when. Concerns about variation traditionally have been confined to the most advanced nodes, where transistor density is highest and where manufacturing processes are still being fine-t... » read more

SiPs And MCMs Broaden Opportunities For Military-Aerospace System Design


Military and aerospace (mil-aero) applications, from satellites and rockets to ships and planes, increasingly require electronic systems and subsystems with high functionality and performance in a small form factor. Meeting these demands poses higher-level challenges for packaging of these microelectronic devices, which needs to be rugged, long-lived, and affordable. Usage of multi-chip modu... » read more

Wafer Shortage Improvement In Sight For 300mm, But Not 200mm


The supply chain for bare wafers is off-kilter. Demand is appreciably higher than the wafer suppliers can keep up with, creating shortages that could last for years. For 300mm starting wafers, the top five big players — SEH and Sumco of Japan, Siltronic of Germany, GlobalWafers of Taiwan, and SK Siltron of Korea — finally took action over the last year, spending billions on new wafer fac... » read more

Week in Review: Manufacturing, Test


Industry Numbers NAND flash memory is forecast to hit US $83 billion this year, an increase of 24%. DRAM is projected to hit $118 billion, up 25%, according to a recent Yole report. Both are historic records. DRAM and NAND revenues are expected to be a $260 billion market in 2027 (combined), with advanced technologies such as EUV lithography, hybrid bonding and 3D DRAM driving this. SEMI in... » read more

Paving The Way To Chiplets


The packaging industry is putting pieces in place to broaden the adoption of chiplets beyond just a few chip vendors, setting the stage for next-generation 3D chip designs and packages. New chiplet standards, and a cost analysis tool for determining the feasibility of a given chiplet-based design, are two new and important pieces. Along with other efforts, the goal is to propel the chiplet m... » read more

Durability And Cost Benefits Drive Mil-Aero Demand For OCPP


Ceramic packages were, for many years, the option of choice for semiconductor prototype assembly, particularly in military-aerospace applications. They are able to withstand high temperatures and can be hermetically sealed. However, they can be costly and, while they allow for rapid assembly of first samples, the final product is typically a plastic package, so the ceramic prototype doesn’t o... » read more

Chiplets Enter The Supercomputer Race


Several entities from various nations are racing each other to deliver and deploy chiplet-based exascale supercomputers, a new class of systems that are 1,000x faster than today’s supercomputers. The latest exascale supercomputer CPU and GPU designs mix and match complex dies in advanced packages, adding a new level of flexibility and customization for supercomputers. For years, various na... » read more

Week In Review: Manufacturing, Test


Chipmakers and OEMs Apple has rolled out its most powerful processor, dubbed the M1 Ultra, a multi-die chip that incorporates the company's new packaging technology. The M1 Ultra is incorporated in Apple’s new Mac Studio desktop. M1 Ultra features a 20-core CPU, a 64-core GPU, and a 32-core Neural Engine. The M1 Ultra also features UltraFusion, Apple’s new packaging architecture. M1 Ult... » read more

Technology Advances, Shortages Seen For Wire Bonders


A surge in demand for IC packages is causing long lead times for wire bonders, which are used to assemble three-fourths of the world’s packages. The wire bonder market doubled last year, alongside advanced packaging’s rise. Wirebonding is an older technology that typically flies under the radar. Still, packaging houses have multitudes of these key tools that help assemble many — but no... » read more

Next-Gen 3D Chip/Packaging Race Begins


The first wave of chips is hitting the market using a technology called hybrid bonding, setting the stage for a new and competitive era of 3D-based chip products and advanced packages. AMD is the first vendor to unveil chips using copper hybrid bonding, an advanced die-stacking technology that enables next-generation 3D-like devices and packages. Hybrid bonding stacks and connects chips usin... » read more

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