tag: reliability

Measuring ISO 26262 Metrics Of Analog Circuitry In ICs
By Mentor, a Siemens Business - 04 Jan, 2018 - Comments: 0

The goals for automotive electronics are zero defective parts per million (0 DPPM), and safe operation during the expected lifetime of the vehicle. The ISO 26262 standard provides procedures and metrics required before delivery to ensure systems can be expected to operate without unreasonable risk. ISO 26262 specifies circuit metrics and minimum values that are design requirements. Since the... » read more

The Trouble With Models
By Ed Sperling - 20 Dec, 2017 - Comments: 0

Models are becoming more difficult to develop, integrate and utilize effectively at 10/7nm and beyond as design complexity, process variation and physical effects add to the number of variables that need to be taken into account. Modeling is a way of abstracting the complexity in various parts of the semiconductor design, and there can be dozens of models required for complex SoCs. Some are ... » read more

Tech Talk: Substrate Noise Coupling
By Ed Sperling - 14 Dec, 2017 - Comments: 0

Roland Jancke, head of the department for design methodology for the Fraunhofer's Engineering of Adaptive Systems Division, talks with Semiconductor Engineering about the impact of substrate noise coupling on reliability of chips and how to deal with this issue. https://youtu.be/7E2rCwYr6-o » read more

Advanced Packaging Is Suddenly Very Cool
By Ed Sperling - 11 Dec, 2017 - Comments: 2

The hottest chip markets today—automotive AI for autonomous and heavily assisted driving, machine learning, virtual and augmented reality—all are beginning to look at advanced packaging as the best path forward for improving performance and reducing power. Over the past four years, which is when 2.5D and fan-out wafer-level packaging first really began garnering interest, these and othe... » read more

Automotive Foundries
By Ed Sperling - 16 Nov, 2017 - Comments: 0

The race to win a piece of the automotive electronics business has now reached the foundry level, and right now it's not clear exactly how this is going to work. This is uncharted territory for everyone. The build-out of electronics for assisted and autonomous driving is brand new. For existing cars, most of the chips being used are off-the-shelf microcontrollers, commodity MEMS sensors, and... » read more

Challenges And Improvement Of Reliability In Advanced Wafer Level Packaging Technology
By STATS ChipPAC - 06 Nov, 2017 - Comments: 0

The number of WLCSP (wafer-level packages) used in semiconductor packaging has experienced significant growth since its introduction in 1998. The growth has been driven primarily by mobile consumer products because of the small form factor and high performance enabled in the package design. And it is also attractive to wearable electronics and IoT products. Although WLCSSP is now a widely ac... » read more

New Power Concerns At 10/7nm
By Ann Mutschler - 16 Oct, 2017 - Comments: 1

As chip sizes and complexity continues to grow exponentially at 7nm and below, managing power is becoming much more difficult. There are a number of factors that come into play at advanced nodes, including more and different types of processors, more chip-package decisions, and more susceptibility to noise of all sorts due to thinner insulation layers and wires. The result is that engineers ... » read more

Reliability Of eWLB For Automotive Radar Applications
By STATS ChipPAC - 09 Oct, 2017 - Comments: 0

With shrinking of chip sizes, Wafer Level Chip Scale Packaging (WLCSP) becomes an attractive and holistic packaging solutions with various advantages in comparison to conventional packages, such as Ball Grid Array (BGA) with flipchip or wirebonding. With the advancement of various fan-out (FO) WLPs, it has been proven to be a more optimal, low cost, integrated and reliable solution compared to ... » read more

Addressing Thermal Reliability In Next-Gen FinFET Designs
By Anusha Prakash - 18 Sep, 2017 - Comments: 0

The next generation of chips on the 10/7nm finFET processes will be able to cram more devices into same area while also boosting performance, but there's a price to pay for that. The 3D fin structures trap heat, so the the temperature rises on the device and there is no way to dissipate that heat. This combination of higher current density, higher performance and higher temperature has a det... » read more

Tech Talk: 7nm Thermal Effects
By Ed Sperling - 14 Sep, 2017 - Comments: 0

ANSYS' Karthik Srinivasan talks about the effect of heat on reliability at advanced process nodes, including self-heating, circuit aging, and how that will affect automotive electronics. https://youtu.be/SS6iAXp0Kn8   Related Tech Talk: 7nm Power Dealing with thermal effects, electromigration and other issues at the most advanced nodes. » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy