tag: RTL

Toward Smarter Design Automation
By Frank Schirrmeister - 28 May, 2015 - Comments: 0

In less than two weeks, the EDA industry will convene for its biggest conference of the year, the Design Automation Conference, again in San Francisco. Last year, I “came clean” with a post called “Confessions Of An ESL-Aholic,” pointing out that beyond high-level synthesis, a significant shift towards a more abstract design description than RTL has not yet happened and that a lot of th... » read more

Physical Lint: Physical Quality Metrics For Your RTL
By Mark Baker - 14 May, 2015 - Comments: 0

Why Analyze Physical Metrics at RTL? The quality of the logic structures generated from RTL has a direct impact on the number of design iterations required to close a design. Additionally, the quality of logic structures generated from RTL has a direct impact on design utilization. These trends are illustrated in Figure 1. Essentially, improving the quality of the logic structures in a d... » read more

Power Reduction At RTL: Data Gating Adders And Multipliers
By Rob Eccles - 20 Apr, 2015 - Comments: 0

In our previous blog, “Low Power Paradox”, we discussed the implications of the move to FinFET technology. Dynamic power is dominant in finFET designs. Several techniques are available to reduce dynamic power consumption. Microarchitecture changes are one method and they can result in significant power savings. One technique that is frequently used is the data gating of adders and m... » read more

Does Fast Simulation Help Debug Productivity?
By Brian Bailey - 09 Apr, 2015 - Comments: 0

It is nice when a reporter manages to get the scoop of the century, and that was the case at a lunch panel hosted by [getentity id="22032" e_name="Cadence"] at the recent Design and Verification Conference (DVCon) in Santa Clara, CA. Brian Bailey, technology editor for Semiconductor Engineer was the moderator for the panel and broke the news to the crowd. Cadence had developed a logic [getkc id... » read more

With Responsibility Comes Power
By Brian Bailey - 12 Feb, 2015 - Comments: 0

The debate continues as to whether [getkc id="106" kc_name="power"] has risen to become a primary design consideration, or if it remains secondary to functionality and performance. What is indisputable is the rise in the importance of both power and energy conservation. As technology improves, additional aspects of the design flow are being affected. With that, the focus for power reduction is ... » read more

Simulation Performance Driven By Model Efficiency
By Jon McDonald - 29 Jan, 2015 - Comments: 0

In real estate it’s all about location, location, location. For system level simulation it’s all about performance, performance, performance. I have heard many opinions on the performance of SystemC and TLM simulations: some positive, some negative, much of the opinion based on hearsay or other unreliable information. I believe the performance of the simulation is mainly driven by the model... » read more

(Low) Power Predictions 2015
By Anand Iyer - 15 Jan, 2015 - Comments: 1

Happy New Year! As we step into the New Year, lots of exciting things are already underway. First of all, the Internet of Things (IoT) is shaping up in a big way as witnessed at CES last week. Advances in devices that can talk to each other and share information are becoming a reality. Automotive applications, medical devices, industry automation, energy distribution and entertainment are all a... » read more

Are Models Holding Back New Methodologies
By Brian Bailey - 23 Oct, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the state of the industry for [getkc id="101" kc_name="modeling"] at abstractions above [getkc id="49" kc_name="RTL"], a factor which has delayed adoption of [getkc id="104" kn_name="virtual prototypes"] and the proliferation of system-level design and hardware/software codesign. Taking part in the discussion were Frank Schirmeister, group director,... » read more

Making Accurate Power Estimates At RTL
By Rob Eccles - 14 Oct, 2014 - Comments: 0

It may seem counterintuitive, but an accurate estimation of power at Register Transfer Level can be made. In this blog, we will learn how it can be done. The main ingredient In order to understand RTL power estimation, let us first consider making the power estimation at gate level. At gate level we have a netlist that contains standard cell instances. These standard cells have been charact... » read more

Tech Talk: Power Optimization II
By Ed Sperling - 13 Oct, 2014 - Comments: 0

Solaiman Rahim, senior director of engineering at Atrenta, talks with Semiconductor Engineering about where to put your efforts to reap the greatest rewards in power reduction and optimization. This is the second of two parts. [youtube vid=OWyzIyEH_pQ] Part one can be viewed here. » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy