Planning For Panel-Level Fan-out

By Mark LaPedus - 21 Nov, 2019 - Comments: 0

Several companies are developing or ramping up panel-level fan-out packaging as a way to reduce the cost of advanced packaging. Wafer-level fan-out is one of several advanced packaging types where a package can incorporate dies, MEMS and passives in an IC package. This approach has been in production for years, and is produced in a round wafer format in 200mm or 300mm wafer sizes. Fan-out... » read more

Panel Fan-out Ramps, Challenges Remain

By Mark LaPedus - 05 Nov, 2018 - Comments: 0

After years of R&D, panel-level fan-out packaging is finally beginning to ramp up in the market, at least in limited volumes for a few vendors. However, panel-level fan-out, which is an advanced form of today’s fan-out packaging, still faces several technical and cost challenges to bring this technology into the mainstream or high-volume manufacturing. Moreover, several companies are d... » read more

Defect Challenges Growing In Advanced Packaging

By Mark LaPedus - 08 Oct, 2018 - Comments: 0

The current defect inspection systems for packaging are running out of steam for the latest advanced packages, prompting the need for new tools in the market. In response, several vendors are rolling out new defect inspection systems for use in various advanced packages, such as 2.5D/3D technologies and fan-out. The new defect inspection systems are more capable than the previous tools, but ... » read more

Inspecting Unpatterned Wafers

By Mark LaPedus - 16 Aug, 2018 - Comments: 1

Unpatterned wafer inspection, which has flown well under the radar for most of the semiconductor industry, is becoming more critical amid the need to find defects earlier in the manufacturing process flow. Finding those defects is getting harder as critical dimensions shrink. It's more difficult to actually detect smaller defects on bare wafers, there is more data to process, and there is mo... » read more

Blog Review: June 20

By Jesse Allen - 20 Jun, 2018 - Comments: 0

Mentor's Randy Allen digs into OpenACC, a collection of directives and routines to help a compiler uncover and schedule parallelism, plus an examination of the GCC implementation's performance. Cadence's Paul McLellan takes a look at the shifting opinions on FD-SOI vs. finFET as Dan Hutcheson of VLSI Research finds most see the two as complementary technologies in his latest survey. Synop... » read more

Litho Options For Panel Fan-out

By Mark LaPedus - 06 Nov, 2017 - Comments: 2

Several packaging houses are inching closer to production of panel-level fan-out packaging, a next-generation technology that promises to reduce the cost of today’s fan-out packages. In fact, ASE, Nepes, Samsung and others already have installed the equipment in their panel-level fan-out lines with production slated for 2018 or so. But behind the scenes, panel-level packaging houses contin... » read more

Cheaper Fan-Outs Ahead

By Mark LaPedus - 07 Aug, 2017 - Comments: 6

Packaging houses continue to ramp up fan-out wafer-level packages in the market, but customers want lower cost fan-out products for a broader range of applications, such as consumer, RF and smartphones. So in R&D, the industry for some time has been developing next-generation fan-out using a panel-level format, a technology that could potentially lower the cost of fan-out. But there are ... » read more

Going Vertical?

By Debra Vogler - 15 Jun, 2017 - Comments: 0

The topic of transistor scaling has been traditionally covered at SEMICON West in its own right. This year’s event, however, will also explore scaling in 3D, as well as using packaging to accomplish similar objectives. Along with traditional transistor scaling, speakers will tackle design and metrology considerations for scaling the package, and address the economic decisions that inform dens... » read more

2.5D, Fan-Out Inspection Issues Grow

By Ed Sperling - 12 May, 2017 - Comments: 0

As advanced packaging moves into the mainstream, packaging houses and equipment makers are ratcheting up efforts to solve persistent metrology and inspection issues. The goal is to lower the cost of fan-outs, [getkc id="82" kc_name="2.5D"] and [getkc id="42" kc_name="3D-IC"], along with a number of other packaging variants consistent with the kinds of gains that are normally associated with Moo... » read more

The Week In Review: Manufacturing

By Mark LaPedus - 20 Jan, 2017 - Comments: 0

Chipmakers 2017 is just getting underway and there appears to be more restructuring in the IC industry. Toshiba is looking to spin off its semiconductor division and Western Digital (WD) plans to take a minority stake, according to Nikkei, which added that Toshiba would sell a 20% stake for 200-300 billion yen ($1.78-$2.65 billion). “The arrangement would provide Toshiba with short term fund... » read more

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Knowledge Centers
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