tag: Samsung Electronics

Technical Paper Round-Up: June 8
By Linda Christensen - 08 Jun, 2022 - Comments: 0

  New technical papers added to Semiconductor Engineering’s library this week. [table id=32 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a ... » read more

High-throughput LHSI Reflectometry Technique For ICU and IWU Measurements of Semiconductor Devices
By Technical Paper Link - 03 Jun, 2022 - Comments: 0

New technical paper titled "Toward realization of high-throughput hyperspectral imaging technique for semiconductor device metrology," from researchers at Samsung Electronics Co. Abstract "Background: High-throughput three-dimensional metrology techniques for monitoring in-wafer uniformity (IWU) and in-cell uniformity (ICU) are critical for enhancing the yield of modern semiconductor manu... » read more

Week In Review: Design, Low Power
By Jesse Allen - 13 May, 2022 - Comments: 0

Tools & IP MIPS announced its first products based on the RISC-V ISA. The eVocore IP cores are designed to provide a flexible foundation for heterogeneous compute, supporting combinations of eVocore processors as well as other accelerators, with a Coherence Manager that maintains L2 cache and system-level coherency between all cores, main memory, and I/O devices. They target high-performan... » read more

Strategies For Faster Yield Ramps On 5nm Chips
By Laura Peters - 12 Apr, 2022 - Comments: 0

Leading chipmakers TSMC and Samsung are producing 5nm devices in high volume production and TSMC is forging ahead with plans for first 3nm silicon by year end. But to meet such aggressive targets, engineers must identify defects and ramp yield faster than before. Getting a handle on EUV stochastic defects — non-repeating patterning defects such as microbridges, broken lines, or missing con... » read more

Week In Review: Manufacturing, Test
By Ed Sperling - 08 Apr, 2022 - Comments: 0

Deals AMD plans to purchase cloud startup Pensando for about US $1.9 billion. In a presentation at the SEMI ISS conference this week, AMD CTO Mark Papermaster described Pensando's technology as a "highly programmable packet-processing engine that allows you to speed up systems designed for the data center." Intel, Micron, Analog Devices and MITRE Engenuity formed an alliance to accelerate c... » read more

Week In Review: Design, Low Power
By Jesse Allen - 01 Apr, 2022 - Comments: 0

Tools Synopsys introduced a new model for using its EDA tools on the cloud. Synopsys Cloud provides pay-as-you-go access to the company's cloud-optimized design and verification products, with pre-optimized infrastructure on Microsoft Azure to address higher levels of interdependencies in chip development. "As more design flows incorporate AI, requiring even more resources, the virtually unlim... » read more

Technical Paper Round-Up: March 22
By Linda Christensen - 22 Mar, 2022 - Comments: 0

New memories, materials, and transistor types, and processes for making those devices, highlighted the past week's technical papers. That includes everything from vertical MoS2 to programmable black phosphorus image sensors and photonic lift-off processes for flexible thin-film materials. Papers continue to flow from all parts of the supply chain, with some new studies out of Pakistan, Seoul... » read more

An Energy-Efficient DRAM Cache Architecture for Mobile Platforms With PCM-Based Main Memory
By Technical Paper Link - 21 Mar, 2022 - Comments: 0

Abstract "A long battery life is a first-class design objective for mobile devices, and main memory accounts for a major portion of total energy consumption. Moreover, the energy consumption from memory is expected to increase further with ever-growing demands for bandwidth and capacity. A hybrid memory system with both DRAM and PCM can be an attractive solution to provide additional capacity ... » read more

Week In Review: Design, Low Power
By Jesse Allen - 04 Mar, 2022 - Comments: 0

Tools & IP Imperas Software introduced the RISC-V Verification Interface (RVVI). The open standard and methodology can be adapted to any configuration permitted within the RISC-V specifications. RVVI defines interfaces between RTL, reference model, and testbench for RISC-V design verification, with the aim of making RISC-V processor DV reusable. It supports multi-hart, superscalar, and out... » read more

Week In Review: Design, Low Power
By Jesse Allen - 25 Feb, 2022 - Comments: 0

Tools & IP Codasip debuted two new customizable low power embedded RISC-V processor cores. To support embedded AI applications, the L31/L11 cores run Google’s TensorFlowLite for Microcontrollers. Codasip Studio tools can be used to customize for specific system, software, and application requirements. Licensing the CodAL description of a Codasip RISC-V core grants customers a full archit... » read more

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