tag: SAQP

Single Vs. Multi-Patterning Advancements For EUV
By Gregory Haley - 20 Jun, 2024 - Comments: 0

As semiconductor devices become more complex, so do the methods for patterning them. Ever-smaller features at each new node require continuous advancements in photolithography techniques and technologies. While the basic lithography process hasn’t changed since the founding of the industry — exposing light through a reticle onto a prepared silicon wafer — the techniques and technology ... » read more

Pathfinding By Process Window Modeling: Advanced DRAM Capacitor Patterning Process Window Evaluation Using Virtual Fabrication
By Coventor - 14 Dec, 2022 - Comments: 0

In advanced DRAM, capacitors with closely packed patterning are designed to increase cell density. Thus, advanced patterning schemes, such as multiple litho-etch, SADP and SAQP processes may be needed. In this paper, we systematically evaluate a DRAM capacitor hole formation process that includes SADP and SAQP patterning, using virtual fabrication and statistical analysis in SEMulator3D. The pu... » read more

Using BDA To to Predict SAQP Pitch Walk
By Technical Paper Link - 08 Nov, 2022 - Comments: 0

A new technical paper titled "Bayesian dropout approximation in deep learning neural networks: analysis of self-aligned quadruple patterning" was published by researchers at IBM TJ Watson Research Center and Rensselaer Polytechnic Institute. Find the technical paper here. Published November 2022.  Open Access. Scott D. Halle, Derren N. Dunn, Allen H. Gabor, Max O. Bloomfield, and Mark Sh... » read more

Insights Into Advanced DRAM Capacitor Patterning: Process Window Evaluation Using Virtual Fabrication
By Qingpeng Wang - 20 Oct, 2022 - Comments: 0

With continuous device scaling, process windows have become narrower and narrower due to smaller feature sizes and greater process step variability [1]. A key task during the R&D stage of semiconductor development is to choose a good integration scheme with a relatively large process window. When wafer test data is limited, evaluating the process window for different integration schemes can... » read more

Using Process Modeling To Enhance Device Uniformity During Self-Aligned Quadruple Patterning
By Timothy Yang - 18 Nov, 2021 - Comments: 0

Despite the growing interest in EUV lithography, self-aligned quadruple patterning (SAQP) still holds many technical advantages in pattern consistency, simplicity, and cost. This is particularly true for very simple and periodic patterns, such as line & space patterns or hole arrays. The biggest challenge of SAQP is the inherently asymmetric mask shape. This asymmetry can create structural ... » read more

Building Predictive And Accurate 3D Process Models
By Pradeep Nanja - 21 Sep, 2020 - Comments: 0

Process engineers and integrators can use virtual process modeling to test alternative process schemes and architectures without relying on wafer-based testing. One important aspect of building an accurate process model is to ensure that the model is calibrated. Having a calibrated model is important, since it provides assurance to the process integrators and engineers that the model will refle... » read more

Metrology Challenges For Gate-All-Around
By Mark LaPedus - 16 Apr, 2020 - Comments: 3

Metrology is proving to be a major challenge for those foundries working on processes for gate-all-around FETs at 3nm and beyond. Metrology is the art of measuring and characterizing structures in devices. Measuring and characterizing structures in devices has become more difficult and expensive at each new node, and the introduction of new types of transistors is making this even harder. Ev... » read more

Controlling Variability Using Semiconductor Process Window Optimization
By Benjamin Vincent - 01 Jul, 2019 - Comments: 0

To ensure success in semiconductor technology development, process engineers must set the allowed ranges for wafer process parameters. Variability must be controlled, so that final fabricated devices meet required specifications. These specifications include critical dimensions, electrical performance requirements, and other device characteristics. Pre-production or ramp-up production Si wa... » read more

Lithography Options For Next-Gen Devices
By Mark LaPedus - 18 Apr, 2019 - Comments: 2

Chipmakers are ramping up extreme ultraviolet (EUV) lithography for advanced logic at 7nm and/or 5nm, but EUV isn’t the only lithographic option on the table. For some time, the industry has been working on an assortment of other next-generation lithography technologies, including a new version of EUV. Each technology is different and aimed at different applications. Some are here today, w... » read more

Improving SAQP Patterning Yield Using Virtual Fabrication And Advanced Process Control
By Benjamin Vincent - 25 Mar, 2019 - Comments: 0

Advanced logic scaling has created some difficult technical challenges, including a requirement for highly dense patterning. Imec recently confronted this challenge, by working toward the use of Metal 2 (M2) line patterning with a 16 nm half-pitch for their 7nm node (equivalent to a 5nm foundry node). Self-Aligned Quadruple Patterning (SAQP) was investigated as an alternative path to Extreme Ul... » read more

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