tag: self-aligned quadruple patterning

Using BDA To to Predict SAQP Pitch Walk
By Technical Paper Link - 08 Nov, 2022 - Comments: 0

A new technical paper titled "Bayesian dropout approximation in deep learning neural networks: analysis of self-aligned quadruple patterning" was published by researchers at IBM TJ Watson Research Center and Rensselaer Polytechnic Institute. Find the technical paper here. Published November 2022.  Open Access. Scott D. Halle, Derren N. Dunn, Allen H. Gabor, Max O. Bloomfield, and Mark Sh... » read more

Using Process Modeling To Enhance Device Uniformity During Self-Aligned Quadruple Patterning
By Timothy Yang - 18 Nov, 2021 - Comments: 0

Despite the growing interest in EUV lithography, self-aligned quadruple patterning (SAQP) still holds many technical advantages in pattern consistency, simplicity, and cost. This is particularly true for very simple and periodic patterns, such as line & space patterns or hole arrays. The biggest challenge of SAQP is the inherently asymmetric mask shape. This asymmetry can create structural ... » read more

N7 FinFET Self-Aligned Quadruple Patterning Modeling
By Coventor - 16 Dec, 2019 - Comments: 0

In this paper, we model fin pitch walk based on a process flow simulation using the Coventor SEMulator3D virtual platform. A taper angle of the fin core is introduced into the model to provide good agreement with silicon data. The impact on various Self-Aligned Quadruple Patterning process steps is assessed. Etch sensitivity to pattern density is reproduced in the model and provides insight on ... » read more

Lithography Options For Next-Gen Devices
By Mark LaPedus - 18 Apr, 2019 - Comments: 2

Chipmakers are ramping up extreme ultraviolet (EUV) lithography for advanced logic at 7nm and/or 5nm, but EUV isn’t the only lithographic option on the table. For some time, the industry has been working on an assortment of other next-generation lithography technologies, including a new version of EUV. Each technology is different and aimed at different applications. Some are here today, w... » read more

N7 FinFET Self-Aligned Quadruple Patterning Modeling
By Coventor - 14 Dec, 2018 - Comments: 0

Authors: Sylvain Baudot, Sofiane Guissi, Alexey P. Milenin, Joseph Ervin, Tom Schram (IMEC and COVENTOR) In this paper, we model fin pitch walk based on a process flow simulation using the Coventor SEMulator3D virtual platform. A taper angle of the fin core is introduced into the model to provide good agreement with silicon data. The impact on various Self-Aligned Quadruple Patterning proces... » read more

Self-Aligned Block And Fully Self-Aligned Via For iN5 Metal 2 Self-Aligned Quadruple Patterning
By Coventor - 29 Mar, 2018 - Comments: 0

This paper assesses Self-Aligned Block (SAB) and Fully Self-Aligned Via (FSAV) approaches to patterning using a iN5 (imec node 5 nm) vehicle and Metal 2 Self-Aligned Quadruple Patterning. We analyze SAB printability in the lithography process using process optimization, and demonstrate the effect of SAB on patterning yield for a (8 M2 lines x 6 M1 lines x 6 Via) structure. We show that FSAV, co... » read more

Improving Patterning Yield At The 5nm Semiconductor Node
By Benjamin Vincent - 29 Mar, 2018 - Comments: 0

Engineering decisions are always data-driven. As scientists, we only believe in facts and not in intuition or feelings. At the manufacturing stage, the semiconductor industry is eager to provide data and facts to engineers based upon metrics such as the quantity of wafers produced per hour and sites/devices tested on each of those wafers. The massive quantity of data generated in semiconduct... » read more

Tech Talk: 7nm Litho
By Ed Sperling - 20 Jul, 2017 - Comments: 2

David Fried, chief technology officer at Coventor, digs into future scaling issues involving multi-patterning and new transistor types. https://youtu.be/FBnYRAL1xKY Related Stories Inside Next-Gen Transistors Coventor’s CTO looks at new types of transistors, the expanding number of challenges at future process nodes & the state of semiconductor development in China. Faster Time T... » read more

New BEOL/MOL Breakthroughs?
By Mark LaPedus - 15 Jun, 2017 - Comments: 1

Chipmakers are moving ahead with transistor scaling at advanced nodes, but it's becoming more difficult. The industry is struggling to maintain the same timeline for contacts and interconnects, which represent a larger portion of the cost and unwanted resistance in chips at the most advanced nodes. A leading-edge chip consists of three parts—the transistor, contacts and interconnects. The ... » read more

The Race To 10/7nm
By Mark LaPedus - 22 May, 2017 - Comments: 4

Amid the ongoing ramp of 16/14nm processes in the market, the industry is now gearing up for the next nodes. In fact, GlobalFoundries, Intel, Samsung and TSMC are racing each other to ship 10nm and/or 7nm technologies. The current iterations of 10nm and 7nm technologies are scaled versions of today’s 16nm/14nm finFETs with traditional copper interconnects, high-k/metal-gate and low-k diele... » read more

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