tag: semiconductor

Foundries See Growth, New Issues In 2019
By Mark LaPedus - 17 Dec, 2018 - Comments: 0

The silicon foundry business is poised for growth in 2019, although the industry faces several challenges across a number of market segments next year. Generally, foundry vendors saw steady growth in 2018, but many are ending the year on a sour note. Weak demand for Apple’s new iPhone XR and a downturn in the cryptocurrency market have impacted several IC suppliers and foundries, causing t... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 14 Dec, 2018 - Comments: 2

Intel Mark Bohr, a senior fellow and director of process architecture and integration at Intel, is retiring, according to the company. Bohr, who will retire at the end of February 2019, held various technology positions during his 41-year career at Intel. Here is a quick bio on Bohr. Others have also recently retired from Intel’s manufacturing unit amid a massive reorganization in the depart... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 07 Dec, 2018 - Comments: 0

Fab tools/manufacturing Lam Research has accepted Martin Anstice’s resignation as chief executive and a member of the board. Lam has named Tim Archer as president and chief executive effective immediately. Archer, who served as Lam’s president and chief operating officer, has been named to the board. One analyst provided a comment on the situation at Lam. “In our view, Mr. Archer is very... » read more

Week In Review: Design, Low Power
By Jesse Allen - 07 Dec, 2018 - Comments: 0

RISC-V Western Digital announced big plans for RISC-V with a new open source RISC-V core, an open standard initiative for cache coherent memory over a network, and an open source RISC-V instruction set simulator. The SweRV Core features a 2-way superscalar design with a 32-bit, 9 stage pipeline core. It has clock speeds of up to 1.8Ghz on a 28mm CMOS process technology and will be used in vari... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 30 Nov, 2018 - Comments: 0

Chipmakers GlobalFoundries has announced that its advanced silicon-germanium (SiGe) offering is available for prototyping on 300mm wafers. GF’s SiGe technology has been shipping on its 200mm production line in Burlington, Vt. The technology, a 90nm SiGe process, is moving to 300mm wafers at GF’s Fab 10 facility in East Fishkill, N.Y. The SiGe technology is called 9HP. “The increasing ... » read more

Week In Review: Design, Low Power
By Jesse Allen - 30 Nov, 2018 - Comments: 0

Tools & IP UltraSoC debuted functional safety-focused Lockstep Monitor, a set of configurable IP blocks that are protocol aware and can be used to cross-check outputs, bus transactions, code execution, and register states between two or more redundant systems. It supports all common lockstep / redundancy architectures, including full dual-redundant lockstep, split/lock, master/checker, and... » read more

5 Best Practices For Successfully Managing An ASIC Supply Chain
By DELTA, a part of FORCE Technology - 05 Nov, 2018 - Comments: 0

Managing an end-to-end ASIC supply chain is one of the primary challenges of chip projects. Not only is the process long and complex, but it involves multiple technologies, dependencies and stakeholders. In this paper, we've assembled five best practices to help you translate ASIC specifications into a final product through a smooth supply chain process, including: Avoid costly time-... » read more

Panel Fan-out Ramps, Challenges Remain
By Mark LaPedus - 05 Nov, 2018 - Comments: 0

After years of R&D, panel-level fan-out packaging is finally beginning to ramp up in the market, at least in limited volumes for a few vendors. However, panel-level fan-out, which is an advanced form of today’s fan-out packaging, still faces several technical and cost challenges to bring this technology into the mainstream or high-volume manufacturing. Moreover, several companies are d... » read more

System-Level Testing – The New Paradigm for Semiconductor Quality Control
By Astronics - 05 Nov, 2018 - Comments: 0

Covering the history and trends of system-level test for semiconductors, this solution brief discusses: The increasing complexities of testing advanced semiconductor integrated devices across a span of applications: automotive, mobile computing, wearables, and more; Semiconductor trends driving necessary shifts in testing methodologies including SiP, SoC, 3D finFETs, heterogeneous compo... » read more

Using DSA With EUV
By Ed Sperling - 05 Nov, 2018 - Comments: 1

James Lamb, deputy CTO for advanced semiconductor manufacturing and corporate technical fellow at Brewer Science, looks at how directed self-assembly can be used to supplement EUV at advanced nodes. https://youtu.be/PItF4egHOxc     See other tech talk videos here » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy