Week In Review: Manufacturing, Test

Intel’s Bohr retires; Intel’s new chip/packaging efforts; trade.


Mark Bohr, a senior fellow and director of process architecture and integration at Intel, is retiring, according to the company. Bohr, who will retire at the end of February 2019, held various technology positions during his 41-year career at Intel. Here is a quick bio on Bohr. Others have also recently retired from Intel’s manufacturing unit amid a massive reorganization in the department, according to a report.


At Intel’s “Architecture Day” this week, top executives from the chip giant revealed next-generation technologies and discussed its strategy.

At the event, Intel demonstrated a range of 10nm-based systems in development. One of the big stars of the event involved IC packaging. The company rolled out the following technologies:

*Intel introduced its next-generation CPU microarchitecture, based on 10nm. “Sunny Cove will be the basis for Intel’s next-generation server and client processors later next year. Sunny Cove features include: enhanced microarchitecture to execute more operations in parallel; and new algorithms to reduce latency,” according to Intel.

*The company unveiled its new Gen11 integrated graphics with a 64 enhanced execution unit, “more than double previous Intel Gen9 graphics (24 EUs), designed to break the 1 TFLOPS barrier. The new integrated graphics will be delivered in 10nm-based processors beginning in 2019,” according to Intel. In addition, the company also reaffirmed its plan to introduce a discrete graphics processor by 2020.

*Intel demonstrated a new 3D packaging technology, called “Foveros,” which enables logic-on-logic integration.

Intel has been developing IC packages for years. For example, Intel has offered a silicon bridge technology called Embedded Multi-die Interconnect Bridge (EMIB), which makes use of a tiny piece of silicon with routing layers that connects one chip to another in an IC package.

What is Foveros? “Foveros is expected to extend die stacking beyond traditional passive interposers and stacked memory to high-performance logic, such as CPU, graphics and AI processors for the first time,” according to Intel. “The technology provides flexibility as designers seek to ‘mix and match’ technology IP blocks with various memory and I/O elements in new device form factors. It will allow products to be broken up into smaller ‘chiplets,’ where I/O, SRAM and power delivery circuits can be fabricated in a base die and high-performance logic chiplets are stacked on top.”

Recently, Intel and others are jumping into chiplets. Meanwhile, Intel expects to launch a range of products using Foveros beginning in the second half of 2019. The first Foveros product will combine a high-performance 10nm compute-stacked chiplet with a low-power 22FFL base die.

Other technologies from Intel were also disclosed. “We’re applying the model today across our engineering organization as we bring innovative new product and technology initiatives to the world next year and into the future,” said Raja Koduri, Intel’s senior vice president of Core and Visual Computing. “Whether it’s the advanced packaging innovation through ‘Foveros’ logic stacking or the ‘One API’ approach to software developers, we’re taking steps to drive sustainable new waves of innovation.”

Several sites, including AnandTech and Tom’s Hardware, provided comprehensive coverage of the event.

Faraday Technology, an ASIC design service and IP provider, announced the availability of its multi-protocol video interface IP on UMC’s 28nm HPC process. The IP solution supports both transmitter (TX) and receiver (RX), featuring a reduced silicon footprint ideal for panel and sensor interfaces, projectors, MFP, DSC, surveillance, AR and VR, and AI applications.

TSMC is building a new 200mm fab in Tainan, which is in southern Taiwan, according to a report.

Cisco Systems is in talks to acquire optical chip maker Luxtera, according to a report from Bloomberg.

SEMI supports the recently announced free-trade negotiations between the U.S. and Japan. Jay Chittooran, public policy manager at SEMI, testified to a U.S. government interagency panel, noting that semiconductor equipment trade between the U.S. and Japan exceeded $7.6 billion in 2017, or one-fifth of all U.S. trade in this segment.

“Continued access to the Japanese market will remain critical for the semiconductor industry and the countless industries that rely on devices enabled by chips,” said Ajit Manocha, president and CEO of SEMI. “A bilateral trade agreement will lead to greater innovation and stronger growth while supporting more high-skill, high-wage jobs.”

Market research
SEMI reported that worldwide sales of new semiconductor manufacturing equipment are projected to increase 9.7% to $62.1 billion in 2018, exceeding the historic high of $56.6 billion set last year. The equipment market is expected to contract 4.0% in 2019 but grow 20.7% to reach $71.9 billion, an all-time high.

According to International Data Corp. (IDC), worldwide smartphone shipments are expected to decline by 3% in 2018 before returning to low single-digit growth in 2019 and through 2022.

Analysts at Strategy Analytics have released their top 10 predictions for 2019.


Gil Russell says:

Hi Mark,

Mark Bohr retiring has to be some sort of indicator of what is going on in Oregon. He held court in the best attended session of the now defunct IDF. The analyst community will sorely miss his presence at Intel. Any comments on 3D XPoint delay and the miss on 10 nm being co-incident?

Gil Russell says:

Hi Mark,
Mark Bohr retiring is a turn for the worse in the analyst community. He was the goto guy on Intel’s processor technology at the now defunct IDF (first indicator of problems in Aloha?). The Analyst Community will sorely miss his ability to communicate Intel’s processor technology.
Any comment on the coincidence of the 10 nm with the 3D XPoint memory.

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