Evaluating The Impact Of STI Recess Profile Control On Advanced FinFET Performance

By Yu De Chen - 21 Oct, 2021 - Comments: 0

Profile variation is one of the most important problems during semiconductor device manufacturing and scaling. These variations can degrade both chip yield and device performance. Virtual fabrication can be used to study profile variation in a very effective and economical manner and avoid process cycle time and wafer cost in the fab. In this short article, we will review the impact of STI (s... » read more

Evaluating The Impact Of STI Recess Profile Control On Advanced FinFET Device Performance

By Coventor - 15 Sep, 2021 - Comments: 1

In this paper, a 5nm FinFET flow was built using the SEMulator3D virtual fabrication platform. Different STI (shallow trench isolation) recess profiles were investigated using the pattern-dependent etch capabilities of SEMulator3D, including changes in trenching/footing profile, fin height and imbalance fin height. The impact of STI recess profile on device performance was then investigated usi... » read more

Re-Engineering The FinFET

By Mark LaPedus - 13 Nov, 2014 - Comments: 0

The semiconductor industry is still in the early stages of the [getkc id="185" kc_name="finFET"] era, but the [getkc id="26" kc_name="transistor"] technology already is undergoing a dramatic change. The fins themselves are getting a makeover. In the first-generation finFETs, the fins were relatively short and tapered. In the next wave, the fins are expected to get taller, thinner and more re... » read more

Ion Implanter Market Heats Up

By Mark LaPedus - 14 Aug, 2014 - Comments: 0

The ion implanter market has been a stable, if not a sleepy, business. The last big event took place in 2011, when Applied Materials re-entered the ion implanter market by acquiring Varian, the world’s leading supplier of these tools. The acquisition gave Applied Materials a commanding 80% share of the implanter business, with the other players fighting for the crumbs. But after year... » read more

A Guide To Advanced Process Design Kits

By Ernest Worthman - 14 Apr, 2014 - Comments: 1

The increasing complexity of design enablement has prompted manufacturers to optimize the design process. New tools and techniques, thanks to next-generation hardware and software, have provided a new platform for semiconductor and wafer design. Advanced PDKs are the solution and have been developed by foundries to optimize the design process and leverage and reuse intellectual property (IP) an... » read more

Overcoming Shallow Trench Isolation

By Kathryn Ta - 20 Jun, 2013 - Comments: 0

By Kathryn Ta To prevent electrical current leaking between adjacent transistors, state-of-the-art microchips feature shallow trench isolation (STI) to isolate transistors from each other. Key steps in the STI process involve etching a pattern of trenches in the silicon, depositing dielectric materials to fill the trenches, and removing the excess dielectric using technologies such as chemical... » read more

Fabless-Foundry Model Under Stress

By Ed Sperling - 26 Jun, 2012 - Comments: 0

By Mark LaPedus The semiconductor roadmap was once a smooth and straightforward path, but chipmakers face a bumpy and challenging ride as they migrate to the 20nm node and beyond. Among the challenges seen on the horizon are the advent of 3D stacking, 450mm fabs, new transistor architectures, multi-patterning, and the questionable availability of extreme ultraviolet (EUV) lithography. ... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer