tag: simulation

What Will The Next-Gen Verification Flow Look Like?
By Ed Sperling - 28 May, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss what's ahead for verification with Daniel Schostak, Arm fellow and verification architect; Ty Garibay, vice president of hardware engineering at Mythic; Balachandran Rajendran, CTO at Dell EMC; Saad Godil, director of applied deep learning research at Nvidia; and Nasr Ullah, senior director of performance architecture at SiFive. What follows are exc... » read more

Introducing The Simulation World Virtual Conference For Multiphysics Verification
By Marc Swinnen - 22 May, 2020 - Comments: 0

The elimination of all live seminars and conferences has been felt particularly acutely by Ansys. The company’s extraordinary breadth of simulation products across many different physics – including fluidics, mechanical, optical, electrical, materials, and semiconductors – means that dozens of events for many different industrial sectors have been cancelled or postponed this year. In r... » read more

Inevitable Bugs
By Brian Bailey - 29 Apr, 2020 - Comments: 3

Are bug escapes inevitable? That was the fundamental question that Oski Technology recently put to a group of industry experts. The participants are primarily simulation experts who, in many cases, help direct the verification directions for some of the largest systems companies. In order to promote free discussion, all comments have been anonymized, distilling the primary thoughts of the parti... » read more

Math And Electronic Design Automation
By Frank Schirrmeister - 23 Apr, 2020 - Comments: 0

Even though our teenage children may not show it the proper appreciation (yet), math is often referred to as the "universal language." And it is, even in EDA. Whenever I’m asked what the heck I do in my day job, I often fall back on analogies—a lot of them refer to building houses. For the geekier ones among us, I have even invoked The Hitchhiker's Guide to the Galaxy's Slartibartfast to ex... » read more

Accelerated Life Testing For Failure Prediction
By Chris South - 09 Apr, 2020 - Comments: 0

By Theresa Duncan and Chris South Product reliability is essential for success, especially for electronic products like printed circuit boards (PCB). Accelerated life testing (ALT) is an expedient and cost-effective solution to determine the reliability and robustness of an electronic product or component. ALT uncovers potential failure risks and quantifies the life characteristics of a p... » read more

Simulation: Balancing Speed And Debug
By Rohit Narkar - 09 Apr, 2020 - Comments: 2

There’s an old saying about simulation: “It’s all about the need for speed.” Simulation is the core technology for functional verification of semiconductors, and the demand for higher runtime performance never ebbs. Larger chips require more complex testbenches and much larger test suites since verification grows exponentially with increase in design size. With the diminishing return an... » read more

New Ways To Optimize Machine Learning
By Bryon Moyer - 02 Apr, 2020 - Comments: 1

As more designers employ machine learning (ML) in their systems, they’re moving from simply getting the application to work to optimizing the power and performance of their implementations. Some techniques are available today. Others will take time to percolate through the design flow and tools before they become readily available to mainstream designers. Any new technology follows a basic... » read more

What Machine Learning Can Do In Fabs
By Mark LaPedus - 25 Mar, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss the issues and challenges with machine learning in semiconductor manufacturing with Kurt Ronse, director of the advanced lithography program at Imec; Yudong Hao, senior director of marketing at Onto Innovation; Romain Roux, data scientist at Mycronic; and Aki Fujimura, chief executive of D2S. What follows are excerpts of that conversation. L-R:... » read more

Building A Safety Verification Flow
By Ed Sperling - 24 Mar, 2020 - Comments: 0

Sal Alvarez, senior manager of application engineering at Synopsys, explains how safety verification differs from functional verification, what changes with failure mode effects analysis, and how to determine and verify the effectiveness of safety features. » read more

Timing Closure At 7/5nm
By Ed Sperling - 17 Mar, 2020 - Comments: 2

Mansour Amirfathi, director of application engineering at Synopsys, examines how to determine if assumptions about design are correct, how many cycles are needed for a particular operation and why this is so complicated, and what happens if signals get out of phase. » read more

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