tag: simulation

Scan Diagnosis
By Ed Sperling - 20 Dec, 2019 - Comments: 1

Jayant D’Souza, product manager at Mentor, a Siemens Business, explains the difference between scan test and scan diagnosis, what causes values in a scan test to change, how this can be used to hone in on the actual cause of a failure in a design, and how to utilize test hardware more efficiently. » read more

Achieving Functional Safety For Autonomous Vehicle SoC Designs
By Mentor, a Siemens Business - 03 Dec, 2019 - Comments: 0

Autonomous vehicle systems will be expected to meet rigorous safety standards regarding many aspects of system design and performance. One set of these standards, known as functional safety, focuses on the safety and reliability of the electrical and electronic systems within the vehicle, and the system-on-chip (SoC) devices in particular. As the complexity of these devices grows, autonomous ve... » read more

Transforming Silicon Bring-Up
By Brian Bailey - 26 Nov, 2019 - Comments: 0

Not too long ago, the return of first silicon from the foundry was a nail-biting moment as power was applied to the chip. Today, better verification methodologies, increased use of emulation, and more mature fabrication practices have transformed how teams utilize first silicon. It is about to be transformed again, and there are some interesting possibilities on the horizon. Much of what use... » read more

Thoroughly Verifying Complex SoCs
By Ann Mutschler - 26 Nov, 2019 - Comments: 0

The number of things that can go wrong in complex SoCs targeted at leading-edge applications is staggering, and there is no indication that verifying these chips will function as expected is going to get any easier. Heterogeneous designs developed for leading-edge applications, such as 5G, IoT, automotive and AI, are now complex systems in their own right. But they also need to work in conju... » read more

Electromagnetic Challenges In High-Speed Designs
By Ed Sperling - 25 Nov, 2019 - Comments: 0

ANSYS’ Anand Raman, senior director, and Nermin Selimovic, product sales specialist, talk with Semiconductor Engineering about how to deal with rising complexity and tighter tolerances in AI, 5G, high-speed SerDes and other chips developed at the latest process nodes where the emphasis is on high performance and low power. » read more

The Challenge Of Defining Worst Case
By Brian Bailey - 14 Nov, 2019 - Comments: 0

Worst case conditions within a chip are impossible to define. But what happens if you missed a corner case that causes chip failure? As the semiconductor market becomes increasingly competitive — startups and systems companies are now competing with established chipmakers — no one can afford to consider theoretical worst cases. Instead, they must intelligently prune the space to make sur... » read more

Power Complexity On The Rise
By Ann Mutschler - 14 Nov, 2019 - Comments: 0

New chip architectures and custom applications are adding significant challenges to chip design and verification, and the problems are becoming much more complex as low power is added into the mix. Power always has been a consideration in design, but in the past it typically involved different power domains that were either on, off, or in some level of sleep mode. As hardware architectures s... » read more

Addressing The Challenges Of Reset Verification In SoC Designs
By Mentor, a Siemens Business - 13 Nov, 2019 - Comments: 0

This paper presents commonly occurring challenges involved in reset tree verification and their solutions. We lay out a three part approach to build a complete solution that combines static analysis of the design structure, RTL simulation with X-propagation, and formal verification. The paper includes results from testing this solution on a customer design. To read more, click here. » read more

Which Verification Engine When
By Ed Sperling - 31 Oct, 2019 - Comments: 0

Frank Schirrmeister, group director for product marketing at Cadence, talks about which tools get used throughout the design flow, from architecture to simulation, formal verification, emulation, prototyping all the way to production, how the cloud has impacted the direction of the flow, and how machine learning will impact verification. » read more

Does System Design Still Need Abstraction?
By Frank Schirrmeister - 24 Oct, 2019 - Comments: 0

About 15 years ago, the assumption in the EDA industry was that system design would be inevitable. The transition from gate-level design to a new entry point at the register transfer level (RTL) seemed complete with logic synthesis becoming well-adopted. The next step seemed to be so obvious at the time: High-level synthesis (HLS) and transaction-based development beyond RTL—also taking into ... » read more

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