Enhancing IO Ring Checks For Consistent, Customizable Verification

By Mentor, a Siemens Business - 25 Nov, 2019 - Comments: 0

The Calibre PERC IO ring checker framework eliminates manual checking by providing a robust DRC-like environment to verify all IO placement rules with sign-off quality. Running on the first LEF/DEF floorplan, the IO ring checker provides early and full coverage of IO ring placement rules, enabling changes with minimal impact on the layout. Fast, accurate debugging and correction ensures that So... » read more

Week in Review: IoT, Security, Autos

By Jeff Dorsch - 25 Oct, 2019 - Comments: 0

Products/Services Rambus reports completing the sale of its Payments and Ticketing businesses to Visa for $75 million in cash. “With 30 years of experience pushing the envelope in semiconductor design, we look toward a future of continued innovation to carry on our mission of making data faster and safer,” Rambus President and CEO Luc Seraphin said in a statement. “Completing this transa... » read more

Scaling Formal Connectivity Checking To Multi-Billion-Gate SoCs With Specification Automation

By OneSpin Solutions - 23 Oct, 2019 - Comments: 0

Connectivity checking is a popular formal verification application. Formal tools can automatically generate assertions using a specification table as input and prove them exhaustively. Simulation-based verification, on the other hand, requires significantly more effort while providing a fraction of the coverage. However, chip complexity is rapidly increasing. ASICs and FPGAs for heterogeneous c... » read more

Analyzing Testbench Design Performance Using Verdi Performance Analyzer

By Synopsys - 09 Oct, 2019 - Comments: 0

Performance continues to be key factor for the design of any complex system-on-chip (SoC). Moreover, complexity is increasing every day, which poses a challenge for engineers to track performance of the design, yet they are tasked to continuously increase chip performance. This paper describes the challenge to measure design performance and explains how Verdi Performance Analyzer enables run ti... » read more

Opposites Attract: IP Standardization vs. Customization

By eSilicon - 25 Sep, 2019 - Comments: 0

Have you had a look lately at an autonomous driving SoC? Have you noticed, besides the cool machine learning stuff, the grocery list of third-party IP that goes into it? It is a long, long list, composed of pieces both big and small and quite diverse. For example, interface and peripheral PHYs and controllers, memories, on-chip interconnects, PVT monitors and PLLs. In some highly-publicized exa... » read more

Best Practices for Traceability of Functional Safety Requirements In Automotive IP & SoCs

By Synopsys - 25 Sep, 2019 - Comments: 0

Automotive functional safety systems continue to incorporate complex features to meet wide range of consumer demands. Developing functional safety systems, including all the components such as the system-on-chip (SoC) and IP, hinges on the ability to meet the stringent automotive functional safety requirements such as definition, implementation, verification, and validation. Functional safety S... » read more

Driving With Chiplets

By Andy Heinig - 24 Sep, 2019 - Comments: 0

The first examples of the upper class of vehicles that can drive autonomously on the highway already have arrived on the market or will be introduced to the market in the coming years. Travel on the highway was selected as the first application because the number of objects that have to be taken into account in front of, next to, and behind the vehicle is manageable. This means the required ... » read more

FPGA Design Tradeoffs Getting Tougher

By Ann Mutschler - 16 Sep, 2019 - Comments: 0

FPGAs are getting larger, more complex, and significantly harder to verify and debug. In the past, FPGAs were considered a relatively quick and simple way to get to market before committing to the cost and time of developing an ASIC. But today, both FPGAs and eFPGAs are being used in the most demanding applications, including cloud computing, AI, machine learning, and deep learning. In some ... » read more

Re-Architecting SoCs For The AI Era

By Arteris - 04 Sep, 2019 - Comments: 0

The growth of artificial intelligence (AI) demands that semiconductor companies re-architect their system on chip (SoC) designs to provide more scalable levels of performance, flexibility, efficiency, and integration. From the edge to data centers, AI applications require a rethink of memory structures, the numbers and types of heterogeneous processors and hardware accelerators, and careful con... » read more

High Voltage Applications.

By UMC - 14 Aug, 2019 - Comments: 0

Today’s high-resolution displays and high data transmission speed have been driving the rapidly growing embedded high voltage (eHV) IC market. UMC supports these applications with extensive and proven eHV technologies, while continuing to invest in research and development to provide more and better solutions to meet current and future requirements for the ever-expanding eHV market. Click... » read more

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tag: SoC

Enhancing IO Ring Checks For Consistent, Customizable Verification

Week in Review: IoT, Security, Autos

Scaling Formal Connectivity Checking To Multi-Billion-Gate SoCs With Specification Automation

Analyzing Testbench Design Performance Using Verdi Performance Analyzer

Opposites Attract: IP Standardization vs. Customization

Best Practices for Traceability of Functional Safety Requirements In Automotive IP & SoCs

Driving With Chiplets

FPGA Design Tradeoffs Getting Tougher

Re-Architecting SoCs For The AI Era

High Voltage Applications.

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