Interconnects Essential To Heterogeneous Integration

By Karen Heyman - 28 Mar, 2024 - Comments: 0

Designing and manufacturing interconnects is becoming more complex, and more critical to device reliability, as the chip industry shifts from monolithic planar dies to collections of chips and chiplets in a package. What was once as simple as laying down a copper trace has evolved into tens of thousands of microbumps, hybrid bonds, through-silicon vias (TSVs), and even junctions for optical ... » read more

Sea Of Processors Use Case

By Movellus - 27 Mar, 2024 - Comments: 0

Core counts have been increasing steadily since IBM's debut of the Power 4 in 2001, eclipsing 100 CPU cores and over 1,000 for AI accelerators. While sea of processor architectures feature a stamp and repeat design, per-core workloads aren't always going to be symmetrically balanced. For example, a cloud provider (AI or compute) will rent out individual core clusters to customers for specialize... » read more

Optimizing Energy At The System Level

By Brian Bailey - 18 Mar, 2024 - Comments: 0

Power is a ubiquitous concern, and it is impossible to optimize a system's energy consumption without considering the system as a whole. Tremendous strides have been made in the optimization of a hardware implementation, but that is no longer enough. The complete system must be optimized. There are far reaching implications to this, some of which are driving the path toward domain-specific c... » read more

FMEDA-Driven SoC Design Of Safety-Critical Semiconductors

By Cadence - 31 Jan, 2024 - Comments: 0

As state-of-the-art electronics propel the automotive, industrial, and aerospace industry into a future of more connectivity and autonomy, the development of safety-compliant semiconductors is critical. The Cadence FMEDA-driven Safety Solution consists of products enhanced for advanced safety analysis, safety verification, and safety-aware implementation for digital driving analog and dig... » read more

Cut Power + Cost 5 – 10x: Integrate FPGA In Your SoC

By Flex Logix - 06 Dec, 2023 - Comments: 0

FPGA chips are high cost devices with a high profit margin for the manufacturer: this goes away when you integrate. FPGA packages are large and expensive because of the large number of very high speed signals that require expensive signal integrity design and packaging layers. When you integrate this goes away. And you save the board area the FPGA package took; and eliminate expensive voltage r... » read more

SoC Integration And Data Transport Architecture Requirements Surge In 2023

By Frank Schirrmeister - 30 Nov, 2023 - Comments: 0

As the holiday season is in full swing, it's retrospection and prediction time! Let's look at what I thought 2023 would look like, review how it turned out, and take a first stab at 2024 predictions. As a spoiler, my biggest surprise was the intensity with which artificial intelligence and machine learning (AI/ML) accelerated since Generative AI was put on the mainstream adoption map last year,... » read more

System-on-Chip Integration Complexity And Hardware/Software Contracts

By Frank Schirrmeister - 26 Oct, 2023 - Comments: 0

From the earliest days of my career, when designing chips, I have always navigated the interface between hardware and software for semiconductor design in my roles. My initial chip designs included video and audio encoding and decoding, supporting standards like MPEG and H.261. As acceleration parts of hardware/software systems, these had many Control and Status Registers (CSRs) to program. The... » read more

A Formal Verification Method To Detect Timing Side Channels In MCU SoCs

By Technical Paper Link - 11 Oct, 2023 - Comments: 0

A technical paper titled “A New Security Threat in MCUs – SoC-wide timing side channels and how to find them” was published by researchers at University of Kaiserslautern-Landau and Stanford University. Abstract: "Microarchitectural timing side channels have been thoroughly investigated as a security threat in hardware designs featuring shared buffers (e.g., caches) and/or parallelism b... » read more

Using Deep Data Analytics To Enhance Reliability Testing The Fast Roadmap for Zero Defects

By proteanTecs - 10 Oct, 2023 - Comments: 0

proteanTecs and ELES have partnered together to enhance reliability testing with deep data analytics. This collaboration enables SoC manufacturers to improve their qualification envelope to achieve lifetime reliability, shorten their root cause analysis time, and reduce operational costs. This innovative approach adds parametric measurements during the stress test in order to accurately and pre... » read more

Arm Total Compute: Engineering For Tomorrow’s Workload

By Arm - 13 Sep, 2023 - Comments: 0

As consumers seek richer and more immersive experiences from their devices, the way compute systems are engineered must continually evolve to keep up. Arm Total Compute takes a solution-focused approach to system-on-chip design, moving beyond individual IP elements to design and optimize the system as a whole to enable more digital immersion experiences. Not only does this white paper dis... » read more

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by Ann Mutschler

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AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

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What Comes After HBM For Chiplets

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Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

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Defining The Chiplet Socket

The industry may have started with the wrong approach for enabling a third-party chiplet ecosystem, but who will step in and fix it?

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tag: SoC

Interconnects Essential To Heterogeneous Integration

Sea Of Processors Use Case

Optimizing Energy At The System Level

FMEDA-Driven SoC Design Of Safety-Critical Semiconductors

Cut Power + Cost 5 – 10x: Integrate FPGA In Your SoC

SoC Integration And Data Transport Architecture Requirements Surge In 2023

System-on-Chip Integration Complexity And Hardware/Software Contracts

A Formal Verification Method To Detect Timing Side Channels In MCU SoCs

Using Deep Data Analytics To Enhance Reliability Testing The Fast Roadmap for Zero Defects

Arm Total Compute: Engineering For Tomorrow’s Workload

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