IP Security Assurance Standard

By Accellera - 14 Oct, 2020 - Comments: 0

This whitepaper is available from the IP Security Assurance (IPSA) Working Group that describes Accellera’s initial proposal to address the industry’s security concerns involving IP integration. Since integrators typically treat IP as a “black box,” vulnerabilities may inadvertently be inserted into an SoC/ASIC. The whitepaper details the objectives of the IPSA standard and its approach... » read more

Protecting Chiplet Architectures With Hardware Security

By Scott Best - 08 Oct, 2020 - Comments: 0

Chiplets are gaining significant traction as they provide compelling benefits for advancing semiconductor performance, costs, and time to market. With Moore’s Law slowing, building more powerful chips translates into building bigger chips. But with chip dimensions pushing up against reticle limits, growing the size of chips is increasingly impractical. Chiplets offer a new path forward by dis... » read more

Secure Silicon Lifecycle Management Architecture For Functional Safety

By Lee Harrison - 08 Oct, 2020 - Comments: 0

The rapid growth of electronics for automotive applications fueled by advanced ADAS systems pose new challenges for complex SoC design and Silicon Lifecycle Management (SLM) in the supply chain as well as in-field monitoring and management of the population of chips. In these modern complex devices, ensuring the correct and safe operation requires not only functional safety to check for reli... » read more

RISC-V: Will There Be Other Open-Source Cores?

By Ed Sperling - 06 Oct, 2020 - Comments: 5

Part 3: Semiconductor Engineering sat down to discuss the business and technology landscape for RISC-V with Zdenek Prikryl, CTO of Codasip; Helena Handschuh, a Rambus Security Technologies fellow; Louie De Luna, director of marketing at Aldec; Shubhodeep Roy Choudhury, CEO of Valtrix Systems; and Bipul Talukdar, North America director of applications engineering at SmartDV. What follows are exc... » read more

Early Verification Of Multi-Cycle Paths And False Paths In Simulation

By Synopsys - 09 Sep, 2020 - Comments: 0

Timing closure is a critical step in the chip development process. The performance and timing of a design must be verified, and any violations must be investigated and resolved. This includes the specification and verification of timing exceptions. This white paper focuses on false paths and multi-cycle paths, the use of Synopsys Design Constraints (SDC) to specify these exceptions, and the “... » read more

CodaCache: Helping to Break the Memory Wall

By Arteris - 04 Aug, 2020 - Comments: 0

As artificial intelligence (AI) and autonomous vehicle systems have grown in complexity, system performance needs have begun to conflict with latency and power consumption requirements. This dilemma is forcing semiconductor engineers to re-architect their system-on-chip (SoC) designs to provide more scalable levels of performance, flexibility, efficiency, and integration. From the edge to data ... » read more

IP Integration Verification At DVClub Europe

By Saša Stamenković - 30 Jul, 2020 - Comments: 0

Most people involved in pre-silicon verification of digital designs and electronic design automation (EDA) know the folks at Test and Verification Solutions (T&VS – now acquired by Tessolve to offer a full VLSI and test service). Among other things, they organize the Verification Futures (VF) conference in the UK and the DVClub Europe meetings. These are highly technical events, with plen... » read more

eFPGAs Vs. FPGA Chiplets

By Ed Sperling - 22 Jul, 2020 - Comments: 0

Embedded FPGAs are a totally different concept from discrete FPGA chiplets, and that is reflected in size, cost, power and performance. Geoff Tate, CEO of Flex Logix, talks about which applications are best for each, how each maximizes power and performance, and why choices will vary greatly by application. Related eFPGA Knowledge Center FPGA Knowledge Center Increasing EFPGA Densit... » read more

Integrating FPGA: Comparison Of Chiplets Vs. eFPGA

By Geoff Tate - 15 Jul, 2020 - Comments: 0

FPGA is widely popular in systems for its flexibility and adaptability. Increasingly, it is being used in high volume applications. As volumes grow, system designers can consider integration of the FPGA into an SoC to reduce cost, reduce power and/or improve performance. There are two options for integrating FPGA into an SoC: FPGA chiplets, which replace the power hungry SERDES/PHYs wit... » read more

Different Roles, Different Tools

By Tommy Mullane - 09 Jul, 2020 - Comments: 1

A question often posed is: does the use of tools and processes change as you go from block level to subsystem and chip level and as you add software to your system on chip (SoC)? And of course, the answer is that things change a lot. The primary differences between designing individual blocks and designing a big chip are that blocks tend to be designed by individual engineers or very small g... » read more

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tag: SoC

IP Security Assurance Standard

Protecting Chiplet Architectures With Hardware Security

Secure Silicon Lifecycle Management Architecture For Functional Safety

RISC-V: Will There Be Other Open-Source Cores?

Early Verification Of Multi-Cycle Paths And False Paths In Simulation

CodaCache: Helping to Break the Memory Wall

IP Integration Verification At DVClub Europe

eFPGAs Vs. FPGA Chiplets

Integrating FPGA: Comparison Of Chiplets Vs. eFPGA

Different Roles, Different Tools

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