tag: stacked die

Multi-Die Packaging Gains Steam
By Si2 - 06 Oct, 2014 - Comments: 0

By Herb Reiter Many readers will be familiar with my extensive background and focus in the emerging field of 3D IC technology, including both 3D stacked die and 2.5 interposer design flows. Now, I am excited to bring my expertise and passion to Silicon Integration Initiative (Si2), where I am now Director of 3D Programs, helping Si2’s members in the Open3D Technical Advisory Board develop pr... » read more

More Than Moore
By Ed Sperling - 01 Oct, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the value of feature shrinks and what comes next with Steve Eplett, design technology and automation manager at [getentity id="22664" e_name="Open-Silicon"]; Patrick Soheili, vice president and general manager of IP Solutions at [getentity id="22242" e_name="eSilicon"]; Brandon Wang, engineering group director at [getentity id="22032" e_name="Cadenc... » read more

Which Comes First?
By Ed Sperling - 25 Sep, 2014 - Comments: 0

Methodologies in IC design typically follow tools. The tools enable the methodologies, and chipmakers' businesses are built around both of them. That has been the rock-solid foundation for the design and production of chips since well before the impenetrable 1-micron wall. But that approach is falling apart at 28nm, and it will continue to crumble at 16/14nm and 10nm. It simply isn't fast en... » read more

Why Multi-Die Integration Really Is On Its Way
By Steve Schulz - 19 Sep, 2014 - Comments: 0

Admit it. You’ve heard a lot about 3D IC’s for years now, and it’s starting to get old. Lots of talk but not much action, you say? Maybe it will never happen, you say? Well, perhaps it’s time to reassess the current situation, reevaluate emerging needs, and reset our “3D” paradigm for the coming multi-die imperative. The problems associated with 3D IC (stacked die) are real and v... » read more

Why Investments At Advanced Nodes Matter
By Ed Sperling - 18 Sep, 2014 - Comments: 0

Despite all the talk about rising costs of development, uncertainties about lithography and talk about the death of Moore’s Law, a record number of companies are developing chips at 16nm/14nm. That may sound surprising, but asking why that’s happening is probably the wrong question. The really critical question is what they’re going to do with those chips. What’s become quite evident... » read more

One-On-One: Mark Bohr
By Mark LaPedus - 18 Sep, 2014 - Comments: 1

Semiconductor Engineering sat down to discuss process technology, transistor trends, chip-packaging and other topics with Mark Bohr, a senior fellow and director of process architecture and integration at Intel. SE: Intel recently introduced chips based on its new 14nm process. Can you briefly describe the 14nm process? Bohr: It’s our second-generation, tri-gate technology. So it has al... » read more

More Than Moore
By Ed Sperling - 15 Sep, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the value of feature shrinks and what comes next with Steve Eplett, design technology and automation manager at [getentity id="22664" e_name="Open-Silicon"]; Patrick Soheili, vice president and general manager of IP Solutions at [getentity id="22242" e_name="eSilicon"]; Brandon Wang, engineering group director at [getentity id="22032" e_name="Cadenc... » read more

Stacked Die Politics, Technology And Tools
By Ed Sperling - 08 Sep, 2014 - Comments: 0

The path to stacking die may look fairly straightforward, but reality is somewhat different. There is a battle raging between foundries and OSATs over who will actually stack and package the die. There is new technology being created that could change the economics of how these die go together. And there is debate about just how ready the tools are to make all of this happen. All of this is ... » read more

Ready To Pounce
By Ed Sperling - 21 Aug, 2014 - Comments: 0

A series of inflection points at 16/14nm and beyond is having a rather unusual effect on the semiconductor industry. Rather than forge ahead with the next nodes to gain an edge and early lead over rivals—the standard formula for success over the past five decades—the entire supply chain is poised on the edge, waiting for someone to make the first move before they take action. The problem... » read more

Different Approaches Emerge For Stacking Die
By Ed Sperling - 21 Aug, 2014 - Comments: 1

The concept of stacking die to shorten wires, improve performance, and reduce the amount of energy required to drive signals has been in research for at least the past dozen years at both IBM and Intel. And depending upon whom you ask, it could be another 2 to 10 years before it becomes a mainstream packaging approach—if it happens at all. At least part of the confusion stems from how you ... » read more

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