tag: stacked die

Is The Stacked Die Ecosystem Stagnating?
By Ann Mutschler - 23 Dec, 2014 - Comments: 0

While the stacked die ecosystem in general is currently status quo, with not much happening in the past year, there is definitely work being done —albeit cautiously—on the design tools side of things. It would be easy to feel impatient that the design tools are not complete and available today for [getkc id="82" comment="2.5D"] and [getkc id="42" comment="3D IC"] implementation until hearin... » read more

Trouble Spots And Optimism For 2015
By Ed Sperling - 18 Dec, 2014 - Comments: 0

Most top executives in the semiconductor industry are bullish about 2015 and even beyond, particularly as the [getkc id="76" comment="Internet of Things"] begins to drive new markets and market mash-ups, and as more semiconductors find their way into markets such as automotive, health-care and manufacturing. But it's not an entirely rosy picture, and top executives point to potential trouble sp... » read more

Is The Stacked Die Ecosystem Stagnating?
By Ann Mutschler - 18 Dec, 2014 - Comments: 2

It is now widely agreed that not much has been happening in terms of adoption for 2.5D interposer and 3D ICs. “It seems like everyone is still at the starting line waiting for the race to begin," said Javier DeLaCruz, senior director of engineering of [getentity id="22242" e_name="eSilicon"]. "Interposer assembly and IP availability for effectively using the [getkc id="82" comment="2.5D IC... » read more

System Bits: Dec. 16
By Ann Mutschler - 16 Dec, 2014 - Comments: 0

High rise chip For decades, the mantra of the semiconductor industry has been ‘smaller, faster, cheaper.’ Stanford researchers are also adding ‘taller’ to the mix, and describing how to build high-rise chips that promise to leapfrog the performance of the single-story logic and memory chips on today's circuit cards. Stanford researchers said their approach would end the ‘logjams�... » read more

See The Internet Of Things…In 3D
By Steve Schulz - 05 Dec, 2014 - Comments: 0

No, you don’t need 3D glasses to experience two of the hottest emerging technology trends in electronics — just take advantage of the longest running conference series on the topic of 3-D integrated circuits. Now in its 11th year, the 3D Architectures for Semiconductor Integration and Packaging conference will take place in San Francisco next week. The event will feature two pre-conference ... » read more

Signal And Power Integrity Cross Paths
By Ed Sperling - 05 Dec, 2014 - Comments: 2

Signal integrity and power integrity historically have been relatively independent issues, and engineers with expertise in one area generally operate independently of the other. But as more power domains are added to conserve energy and allow more features, as voltages are reduced to save battery life, and as dynamic power becomes more of a concern at advanced nodes, these worlds are suddenly m... » read more

The Internet Of Cores
By Brian Bailey - 20 Nov, 2014 - Comments: 0

Ever since the birth of the third-party [getkc id="43" comment="IP"] market, there has been a desire for plug-and-play compatibility between cores. Part of the value proposition of reuse is that a block has been used before, and has been verified and validated by having been implemented in silicon. By re-using the core, many of these tasks no longer land on the [getkc id="81" kc_name="SoC"] dev... » read more

An Inside Look At The GlobalFoundries-IBM Deal
By Ed Sperling - 20 Nov, 2014 - Comments: 3

GlobalFoundries' proposed acquisition of IBM Microelectronics is the kind of deal that will have business schools talking for many years to come—a gargantuan combination of expertise and technology, built on the back of high-profile business successes and failures, long-running legal struggles and global politics—with far-reaching implications for all parts of the semiconductor supply chain... » read more

Memory Directions Uncertain
By Brian Bailey - 28 Oct, 2014 - Comments: 1

Semiconductor Engineering sat down with a panel of experts to find out what is happening in world of memories. Taking part in the discussion are [getperson id="11073" comment="Charlie Cheng"], chief executive officer at [getentity id="22135" e_name="Kilopass Technology"]; Navraj Nandra, senior director of marketing for Analog/Mixed signal IP, embedded memories and logic libraries at [getentity ... » read more

The Week In Review: Design
By Ed Sperling - 24 Oct, 2014 - Comments: 0

IP Cadence rolled out a portfolio of stacked die memory verification IP to support Wide I/O-2, Hybrid Memory Cube, high-bandwidth memory, and DDR4-3DS. Included are direct memory access for read, write, save, preload and comparison of memory contents, assertions, error configurability, and a built-in address manager. ARM rolled out additions to its enterprise-class SoC interconnects for qua... » read more

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