tag: Synopsys

Blog Review: Nov. 27
By Jesse Allen - 27 Nov, 2019 - Comments: 0

Arm's Ben Fletcher digs into what's needed to make wireless 3D integration a reality from a tool to automate the design and optimization process for inductors used in wireless 3D-ICs to exploring how the data can be encoded in the transceiver to reduce power consumption. Cadence's Paul McLellan listens in as Eli Singerman of Intel explains the importance of platform security and why firmware... » read more

Static Verification Of Low Power Designs
By Himanshu Bhatt - 26 Nov, 2019 - Comments: 0

Are there any chips designed today that don’t have limitations on their power consumption? For smartphones and tablets, increasing the time between charges is a clear product differentiator and a frequent design goal. Power consumption is also an issue for Internet-of-Things (IoT) devices, many of which are in inaccessible locations where battery replacement or recharge is difficult. Even com... » read more

Transforming Silicon Bring-Up
By Brian Bailey - 26 Nov, 2019 - Comments: 0

Not too long ago, the return of first silicon from the foundry was a nail-biting moment as power was applied to the chip. Today, better verification methodologies, increased use of emulation, and more mature fabrication practices have transformed how teams utilize first silicon. It is about to be transformed again, and there are some interesting possibilities on the horizon. Much of what use... » read more

Thoroughly Verifying Complex SoCs
By Ann Mutschler - 26 Nov, 2019 - Comments: 0

The number of things that can go wrong in complex SoCs targeted at leading-edge applications is staggering, and there is no indication that verifying these chips will function as expected is going to get any easier. Heterogeneous designs developed for leading-edge applications, such as 5G, IoT, automotive and AI, are now complex systems in their own right. But they also need to work in conju... » read more

Using PCIe Real World Interface For High-Speed Hybrid Prototyping
By Synopsys - 25 Nov, 2019 - Comments: 0

This white paper highlights a novel approach to hybrid prototyping using a PCIe interface between the HAPS FPGA-based prototyping and the Virtualizer virtual prototyping. The use of PCIe real world interface helps to deliver a prototyping system, running fast enough to enable embedded software development and hardware-software co-validation in the shortest possible time. The hybrid prototyping ... » read more

Week In Review: Design, Low Power
By Jesse Allen - 22 Nov, 2019 - Comments: 1

Accellera formed the Universal Verification Methodology Analog/Mixed-Signal Working Group (UVM-AMS WG), which will work to develop a standard that will provide a unified analog/mixed-signal verification methodology based on UVM to improve the verification of AMS integrated circuits and systems. “Our objective is to standardize a method to drive and monitor analog/mixed-signal nets within UVM,... » read more

Week In Review: IoT, Security, Automotive
By SE Staff - 22 Nov, 2019 - Comments: 0

Automotive Porsche’s electric race car, the 99X Electric, used ANSYS Technology’s system-level simulation solutions to create an advanced electric powertrain. The powertrain is also being adapted for use in Porsche’s consumer electric cars. "ANSYS system-level simulations are instrumental for optimizing the Porsche E-Performance Powertrain's motor, gearbox, power electronics and control ... » read more

Die-To-Die Connectivity
By Ed Sperling - 22 Nov, 2019 - Comments: 0

Manmeet Walia, senior product marketing manager at Synopsys, talks with Semiconductor Engineering about how die-to-die communication is changing as Moore’s Law slows down, new use cases such as high-performance computing, AI SoCs, optical modules, and where the tradeoffs are for different applications.   Interested in more Semiconductor Engineering videos? Sign-up for our YouTu... » read more

Blog Review: Nov. 20
By Jesse Allen - 20 Nov, 2019 - Comments: 0

Arm's Ben Fletcher points to research into a new low-cost alternative to through-silicon vias in 3D stacked ICs, particularly cost-sensitive IoT designs, where communication between silicon layers is completely wireless. Cadence's Paul McLellan checks in on the progress of DARPA's OpenROAD project to build a no-human-in-the-loop open source EDA flow for leading-edge nodes. Mentor's Colin ... » read more

Why Standard Memory Choices Are So Confusing
By Ann Mutschler - 19 Nov, 2019 - Comments: 0

System architects increasingly are developing custom memory architectures based upon specific use cases, adding to the complexity of the design process even though the basic memory building blocks have been around for more than half a century. The number of tradeoffs has skyrocketed along with the volume of data. Memory bandwidth is now a gating factor for applications, and traditional memor... » read more

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