tag: Synopsys

GPUs May Speed UP EDA Algorithms
By Ann Mutschler - 25 Jul, 2013 - Comments: 1

The sequential EDA algorithms of old cannot keep pace with increasing design complexity, which is driving the industry to look at parallelism and other computational architectures such as the graphical processing unit (GPU). A 10X or 20X speedup for gate-level simulations means that a test that runs today in a week will run in less than a day, and a test that runs today in a month will run i... » read more

Raising The IP Abstraction Level
By Ed Sperling - 25 Jul, 2013 - Comments: 0

By Ed Sperling An increasing reliance on commercial and re-used IP and more emphasis placed on software development is adding even more pressure onto semiconductor design teams to figure out the benefits and limitations of myriad possible choices earlier in the design process. Design teams already are under pressure to meet increasingly tighter market deadlines, and it is stressing every pa... » read more

DFTMAX Compression Shared I/O
By Various Writers - 25 Jul, 2013 - Comments: 0

A significant design trend in recent years has been the widespread use of ARM multicore processors in systems-on-chip (SoCs). Designers’ ability to easily and cost-effectively employ multiple, high-performance embedded processors to meet the computational demands of the end application has helped fuel the explosive growth in mobile computing, networking infrastructure, and digital infotainmen... » read more

DFTMAX Compression Shared I/O
By Various Writers - 25 Jul, 2013 - Comments: 0

A significant design trend in recent years has been the widespread use of ARM multicore processors in systems-on-chip (SoCs). Designers’ ability to easily and cost-effectively employ multiple, high-performance embedded processors to meet the computational demands of the end application has helped fuel the explosive growth in mobile computing, networking infrastructure, and digital infotainmen... » read more

Blog Review: July 24
By Ed Sperling - 24 Jul, 2013 - Comments: 0

By Ed Sperling Mentor’s Harry Foster unleashes part six of the Wilson Research Group functional verification study, this segment digging deeper into the time spent in verification. The numbers have surpassed time spent on the design side, which either means the front-end tools are getting better or the verification problem is becoming more difficult. Cadence’s Brian Fuller interviews I... » read more

The Week In Review: July 19
By Ed Sperling - 19 Jul, 2013 - Comments: 0

By Ed Sperling Synopsys rolled out a 28nm data converter IP portfolio for analog-to-digital and digital-to-analog converters, as well as integrated PLLs. Synopsys says the new architecture saves up to 76% of the power and 86% of area. Mentor Graphics added intelligent software-driven verification to its functional verification platform. New is the ability to automatically generate embedded ... » read more

Experts At The Table: SoC Prototyping
By Ann Mutschler - 19 Jul, 2013 - Comments: 0

By Ann Steffora Mutschler System-Level Design sat down to discuss SoC prototyping with Hillel Miller, pre-silicon verification/emulation manager at Freescale Semiconductor; Frank Schirrmeister, group director, product marketing, system development suite at Cadence; and Mick Posner, director of product marketing at Synopsys. What follows are excerpts of that conversation. SLD: When it comes... » read more

A Tale Of Two Standards
By Ed Sperling - 18 Jul, 2013 - Comments: 0

By Ed Sperling It could well be one of the strangest developments in standards history. Two competing standards for power formats were rolled out in the middle of the last decade and aside from a few cries of foul they fell below the radar screen of most chip designers and architects for a half-dozen years. Fast forward to the present and the Common Power Format (CPF) and Unified Power Form... » read more

Experts At The Table: Changes In The Ecosystem
By Ed Sperling - 15 Jul, 2013 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down with Michael Buehler-Garcia, director of design solutions marketing at Mentor Graphics; Seow Yin Lim, group director for marketing at Cadence; Kevin Kranen, director of strategic alliances at Synopsys, and Tom Quan, director at TSMC. What follows are excerpts of that conversation. SMD: Does the increasing collaboration in the ecos... » read more

Experts At The Table: SoC Prototyping
By Ann Mutschler - 12 Jul, 2013 - Comments: 0

By Ann Steffora Mutschler System-Level Design sat down to discuss SoC prototyping with Hillel Miller, pre-silicon verification/emulation manager at Freescale Semiconductor; Frank Schirrmeister, group director, product marketing, system development suite at Cadence; and Mick Posner, director of product marketing at Synopsys. What follows are excerpts of that conversation. SLD: Is it possib... » read more

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