tag: Synopsys

Continuous, Connected And Concurrent Verification
By Ed Sperling - 28 Mar, 2013 - Comments: 0

By Ed Sperling It’s a wonder that any electronic system works as intended, or that it continues to work months or years after it is sold. The reason: SoCs have become so complex that no verification coverage model is sufficient anymore, no methodology covers every aspect of verification, and no single tool or even collection of tools can catch every bug or prevent them from being there in th... » read more

Experts At The Table: Verification Strategies
By Ed Sperling - 28 Mar, 2013 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss verification strategies and changes with Harry Foster, chief verification scientist at Mentor Graphics: Janick Bergeron, verification fellow at Synopsys; Pranav Ashar, CTO at Real Intent; Tom Anderson, vice president of marketing at Breker Verification Systems; and Raik Brinkmann, president and CEO of OneSpin Solutions. What follows are e... » read more

Network Software Bring Up
By Tom De Schutter - 28 Mar, 2013 - Comments: 0

By Tom De Schutter With their latest Cortex-A processors, and especially the ARMv8 Cortex-A57 processor, ARM has provided the right scalability and performance required for network applications. Porting and developing software for these multicore/multi-cluster designs, however, is not a trivial task and cannot be done as an afterthought. That is the topic that Robert Kaye from ARM and I addres... » read more

Observation Post
By Pranav Ashar - 28 Mar, 2013 - Comments: 0

By Pranav Ashar After attending the 2013 Design and Verification Conference (DVCon) in San Jose, Calif., I have compiled notes as both an observer and a panel participant. Here are my observations: Wally Rhines, CEO of Mentor Graphics, gave the keynote presentation: Accelerating EDA Innovation Through SoC Design Methodology Convergence. Logically and effectively he made the case that SoC in... » read more

Staying Neutral
By Kurt Shuler - 28 Mar, 2013 - Comments: 0

By Kurt Shuler It’s official: The great IP land grab has begun. The process actually has been taking place gradually, but has accelerated with Imagination Technologies’ acquisition of MIPS last year and, most recently, Cadence’s acquisition of Tensilica. For makers of semiconductors, four competing IP behemoths are emerging after years of fragmentation within the semiconductor IP indu... » read more

Market Realities
By Ed Sperling - 28 Mar, 2013 - Comments: 0

The speculation about EDA’s future—will it consolidate, will it be incorporated into large IDMs or foundries—has surfaced again. The reason this time is that EDA is in a retrenchment period as the semiconductor industry grapples with increasing complexity, multiple options ranging from multi-patterning to stacked die to more third-party IP, and the rising cost of complex SoCs at the mo... » read more

Physical Verification Of FinFETs And Fully Depleted SOI
By Various Writers - 28 Mar, 2013 - Comments: 0

It has become very difficult to effectively shrink traditional bulk planar transistors below 20nm due to physical effects that become dominant in very short conduction channels. The major impediment is an unacceptable rise in power consumption due to significant leakage currents. New transistor architectures are being adopted that offer a solution for these short-channel effects and allow trans... » read more

Experts At The Table: The Trouble With Low-Power Verification
By Ed Sperling - 22 Mar, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss low-power verification with Leah Clark, associate technical director at Broadcom; Erich Marschner, product marketing manager at Mentor Graphics; Cary Chin, director of marketing for low-power solutions at Synopsys; and Venki Venkatesh, senior director of engineering at Atrenta. What follows are excerpts of that conversat... » read more

A Balancing Act
By Ann Mutschler - 14 Mar, 2013 - Comments: 0

By Ann Steffora Mutschler If you stay current on data center trends, you are well-versed on the fact that Intel reported last June energy proportionality has effectively doubled server efficiency and workload scaling beyond what Moore’s Law predicted. What does this have to do with power management of SoCs? Cary Chin, director of marketing for low-power solutions at Synopsys, said tha... » read more

Moore’s Law 2.0
By Ed Sperling - 14 Mar, 2013 - Comments: 0

By Ed Sperling Doubling the number of transistors on a piece of silicon every 18 to 24 months used to be synonymous with engineering progress, but as the semiconductor world migrates from processors to SoCs the fundamental basis of Moore’s Law is losing its meaning. Even its famous timetable is slipping. For one thing, it’s simply too expensive and difficult to migrate from one node to ... » read more

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