tag: Synopsys

Hot Stuff
By Ann Mutschler - 14 Mar, 2013 - Comments: 0

By Ann Steffora Mutschler When it comes to thermal modeling, which has been practiced for many years, the challenges are daunting. The good news is that approaches are emerging as challenges increased with smaller process nodes and design complexity. Viewed from a number of viewpoints—transistor, chip, package, board and system—thermal models traditionally have been created from m... » read more

Let The IP Wars Begin
By Ed Sperling - 14 Mar, 2013 - Comments: 0

y Ed Sperling Nature abhors a vacuum. Customers abhor a monopoly. It appears both problems are now being solved in the EDA world—assuming approval by regulatory agencies, of course. There have been two concerns facing chipmakers in regards to third-party IP. One is political. Most large companies spent millions of dollars and thousands of frustrating man-hours developing their own interna... » read more

There Can Be Only One
By Synopsys - 14 Mar, 2013 - Comments: 0

By Cary Chin The tagline of the 1986 fantasy film “Highlander” implies that, at least in some instances, we eventually will arrive at a single, best solution for our problems. In the case of low-power design, the most obvious application of the phrase is in the standardization of low power intent formats, where the Unified Power Format (UPF) and the Common Power Format (CPF) have been lock... » read more

Experts At The Table: The Trouble With Low-Power Verification
By Ed Sperling - 14 Mar, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss low-power verification with Leah Clark, associate technical director at Broadcom; Erich Marschner, product marketing manager at Mentor Graphics; Cary Chin, director of marketing for low-power solutions at Synopsys; and Venki Venkatesh, senior director of engineering at Atrenta. What follows are excerpts of that conversat... » read more

Experts At The Table: Verification Strategies
By Ed Sperling - 08 Mar, 2013 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss verification strategies and changes with Harry Foster, chief verification scientist at Mentor Graphics: Janick Bergeron, verification fellow at Synopsys; Pranav Ashar, CTO at Real Intent; Tom Anderson, vice president of marketing at Breker Verification Systems; and Raik Brinkmann, president and CEO of OneSpin Solutions. What follows are ex... » read more

Surprises Abound As Subsystem IP Gains Prominence
By The SE Staff - 28 Feb, 2013 - Comments: 0

What’s new in the world of subsystem intellectual property? To find out, System-Level Design sat down with Richard Wawrzyniak, senior market analyst for ASICs and SoCs at Semico Research Corp. What follow are excerpts of that conversation. SLD: You mentioned that the cost of semiconductor intellectual property (IP) at 20nm and below is increasing. Why is that? Wawrzyniak: The reason is c... » read more

Experts At The Table: Verification Strategies
By Ed Sperling - 28 Feb, 2013 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss verification strategies and changes with Harry Foster, chief verification scientist at Mentor Graphics: Janick Bergeron, verification fellow at Synopsys; Pranav Ashar, CTO at Real Intent; Tom Anderson, vice president of marketing at Breker Verification Systems; and Raik Brinkmann, president and CEO of OneSpin Solutions. What follows are ex... » read more

Have You Had A V8 today?
By Nithya Ruff - 28 Feb, 2013 - Comments: 0

By Nithya Ruff The quick road to the recommended daily allowance of vegetables and fruits is often a bottle of V8. It’s quick, nutritious, and it makes us feel less guilty about any of our nutritional imbalances. It makes us feel virtuous, because we have done something good for our body today. So why do we postpone the inevitable? By this I mean developing new software for a new piec... » read more

Designing with FinFETs: The Opportunities and the Challenges
By Various Writers - 28 Feb, 2013 - Comments: 0

With the help of double-patterning and other advanced lithography techniques, CMOS technology continues to scale to 20-nanometer (nm) and beyond. Yet, because of their superior attributes, FinFETs are replacing planar CMOS technology as the device technology of choice at these advanced nodes. In particular, FinFETs demonstrate better results in the areas of performance, leakage and dynamic powe... » read more

Verifying Complex Chips
By Ed Sperling - 27 Feb, 2013 - Comments: 0

System-Level Design talks about what's changing in SoC verification with Janick Bergeron, verification fellow at Synopsys; Harry Foster, chief verification scientist at Mentor Graphics; Pranav Ashar, chief technology officer at Real Intent; Raik Brinkmann, president and CEO of OneSpin Solutions, and Tom Anderson, vice president of marketing at Breker Verification Systems. [youtube vid=DzDYyf... » read more

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