tag: Synopsys

Big Rocks First
By Synopsys - 14 Feb, 2013 - Comments: 0

By Cary Chin Up on the wall in the hallway by the printer at my office, there’s an article by a management consultant entitled, “PUT THE BIG ROCKS IN FIRST!” It describes the demonstration that has been conducted and described many times by many consultants and motivational speakers over the years. Starting with an empty bucket, place large rocks in the bucket until it is full. Repeat by... » read more

Experts At The Table: Low-Power Verification
By Ed Sperling - 09 Feb, 2013 - Comments: 0

Low-Power Engineering sat down to discuss the problems of identifying and verifying power issues with Barry Pangrle, solutions architect for low-power design at Mentor Graphics; Krishna Balachandran, director of low-power verification marketing at Synopsys; Kalar Rajendiran, senior director of marketing at eSilicon; Will Ruby, senior director of technical sales and support at Apache Design; and... » read more

SoC Architects Face Big Challenges
By Ed Sperling - 31 Jan, 2013 - Comments: 0

By Ann Steffora Mutschler While the geometries of advanced node processes such as 28nm and below may not greatly impact SoC architectures, the complexity enabled by the leading edge brings intense challenges all the same. With the ability to put more transistors onto a chip come new possibilities such as the increasing use of multi-core architectures and lots of integrated hardware en... » read more

Mixing It Up
By Ed Sperling - 31 Jan, 2013 - Comments: 0

By Ann Steffora Mutschler To enable the next level of productivity in the verification space, certain tools need to be combined and integrated in a very meaningful way. The concept is far from new. This happened on the RTL to GDS front between synthesis and place and route. The tools work very closely and there is bi-directional collaboration. It also happened in the functional verification... » read more

Cost Per Transistor Gets Fuzzier
By Ed Sperling - 31 Jan, 2013 - Comments: 0

By Ed Sperling Cost per transistor always has been a major reason for chipmakers to migrate to the next process node. By shrinking transistors and adding more logic, performance usually gets a boost. Moreover, that usually provides enough engineering wiggle room to add some improvements in energy efficiency. The basic assumption that you can double the number of transistors every 24 months,... » read more

Hybrid Prototype Benefits
By Nithya Ruff - 31 Jan, 2013 - Comments: 0

By Troy Scott This month Nithya asked me to contribute a post on hybrid prototyping and add some color to how design teams have been benefiting from integration between virtual and FPGA-based prototypes. It’s been about six months since Synopsys announced the availability of a data exchange, which links a Virtualizer Development Kit (VDK) to the HAPS FPGA-based prototyping system based on AM... » read more

Changes In The Supply Chain
By Ed Sperling - 31 Jan, 2013 - Comments: 0

Runaway complexity in design, implementation, verification and manufacturing is being mirrored across an increasingly complex supply chain. Now the question is what to do about it. Complexity is being driven by the continued shrinking of feature sizes and the clamor for more functionality to leverage the real estate that becomes available with each new process node. But the increased density... » read more

Managing Functional Verification Projects
By Various Writers - 31 Jan, 2013 - Comments: 0

The adoption of advanced verification languages and methodologies requires evolution of project management techniques in addition to the change in engineering practices. Managers must be able to assess and manage key project elements such as team expertise, verification methodology, verification IP (VIP) selection and environment setup to successfully deploy high-level verification environments... » read more

ESL Challenges
By Ed Sperling - 26 Jan, 2013 - Comments: 0

System-Level Design talks about the challenges of ESL with Cadence's Ran Avinun, Synopsys' Johannes Stahl, Mentor Graphics' Thomas Bollaert and Forte Design Systems' Brett Cline.   [youtube vid=HftMM71Epqo] » read more

Reducing The Drama In DFM
By Ed Sperling - 24 Jan, 2013 - Comments: 0

By Ann Steffora Mutschler For reducing cycle time of DFM checks prior to manufacturing, pattern matching is a topic of great excitement as of the past few manufacturing nodes. The idea behind the technology is that there are certain patterns in the physical layout of the chip, which unless they are addressed, won’t come out right. That’s what causes the drama, observed Saleem Haider, se... » read more

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