tag: Synopsys

Making Quality A Top Priority in Next-Generation Designs
By Cheryl Ajluni - 25 Jun, 2009 - Comments: 0

By Cheryl Ajluni With system design such a complicated task these days, it is increasingly likely that designers will inadvertently overlook some details of the design process, or worse yet, simply not have the time to address them adequately. Time is readily spent focusing on things like performance, area, timing, and power, but what about something a bit more esoteric in nature—namely, qu... » read more

Custom IC Design: They Call This Progress?
By Ed Sperling - 25 Jun, 2009 - Comments: 0

By Ed Sperling For decades, analog and digital engineers have lived in completely separate worlds. The lines are blurring between those worlds, though, in complex SoCs. So far, the transition has been difficult, and most engineers predict it will get worse at future process nodes. The basic problem is that each world has functioned independently of the other from the start. They use different... » read more

Formal Verification 101
By Various Writers - 27 May, 2009 - Comments: 0

By Clive "Max" Maxfield The first time I came into contact with the concepts of a digital hardware description language (HDL) and digital logic simulation, I inherently understood how it all "worked." The idea that the statements in the modeling language acted in a concurrent manner just seemed to make sense. By comparison, trying to wrap my brain around formal verification has always mad... » read more

Less Room For Error
By Ed Sperling - 13 May, 2009 - Comments: 0

By Ed Sperling Say goodbye to fat design margins in advanced SoCs. The commonly used method of adding extra performance or area into semiconductors to overcome variability in manufacturing processes or timing closure issues has begun to create problems of its own. While there was plenty of slack available at 90nm, adding margins at 45nm and 32nm disrupts performance or eats into an increasing... » read more

How Many Power Islands Is Too Many?
By Ed Sperling - 13 May, 2009 - Comments: 0

By Ed Sperling Power domains, also known as power islands, have become to design engineers what multiple cores are to processor architects. They can serve a purpose, namely reducing static current leakage and saving battery life. But they also can add so much complexity that they can make it almost impossible to get a new chip out the door. Just as there has been talk of hundreds of cores, th... » read more

Moore’s Law Splinters
By Ed Sperling - 28 Apr, 2009 - Comments: 0

By Ed Sperling Moore’s Law continues progressing at a rate of one node every two years or so, but the number of companies that are adhering to that schedule is becoming much harder to pinpoint. Even the nodes themselves are becoming fuzzy. While Intel is looking at 32nm as the next node after 45nm, TSMC is looking at 28nm as the next node after 40nm. And there are likely to be extensions wi... » read more

Taming The Multicore Beast
By Ed Sperling - 27 Mar, 2009 - Comments: 0

By Ed Sperling Multicore chips are here to stay. Now what? That question is echoing up and down the ranks of tools vendors, design engineers, software developers and even among people who measure the performance and efficiency of semiconductors. There is now a Multicore Expo and a Multicore Association that includes a who’s who of electronics. And there are lots of working groups developing... » read more

Thinking Digital To Design Analog, And Vice Versa
By Ed Sperling - 27 Mar, 2009 - Comments: 0

By Ed Sperling Until several years ago, analog was a world apart from digital. Analog engineers could comfortably avoid many of the issues of Moore’s Law, viewing it as a costly bad habit with an equally bad outcome. Most analog engineers gloated privately that they could still develop chips at 250nm, or at worst 130nm, while their digital counterparts were struggling to keep up with is... » read more

Exploring The Use Of Virtual Platforms At The Electronic System Level
By Cheryl Ajluni - 27 Mar, 2009 - Comments: 0

By Cheryl Ajluni System design is hard. That should not come as a surprise to anyone these days. With design geometries shrinking and device complexity on the rise, this fact is not likely to change anytime soon. One concept for easing that burden for system-level designers is the virtual platform. Granted, the concept itself is nothing new, but today it is being employed in ever more creativ... » read more

Trends in System-Level Prototyping
By Various Writers - 27 Mar, 2009 - Comments: 0

By Clive Maxfield One problem with electronics is that certain terms can mean different things, depending on who one is talking to at the time. Even worse, some terms have a tendency to evolve over time. This means that when we are presented with a topic like "Trends in System-Level Prototyping," before leaping headfirst into the fray, it may be a good idea to first define exactly what we mean... » read more

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