tag: Synopsys

Experts At The Table: Low-Power Verification
By Ed Sperling - 16 Aug, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss power format changes with Sushma Hoonavera-Prasad, design engineer in Broadcom’s mobile platform group; John Biggs, consultant engineer for R&D and co-founder of ARM; Erich Marschner, product marketing manager at Mentor Graphics; Qi Wang, technical marketing group director at Cadence; and Jeffrey Lee, corporate ap... » read more

Can Mask Data Prep Tools Manage Data Glut?
By Ann Mutschler - 15 Aug, 2013 - Comments: 0

By Ann Steffora Mutschler The trend to reduce critical dimension sizes has in turn increased design file sizes, especially with the addition of optical proximity correction (OPC) steps. This extra data translates to a bigger burden to be processed downstream in the flow on the way to the mask writer. At 28nm, design post-OPC data files sizes reach hundreds of gigabytes. With 20nm and below ... » read more

Blog Review: Aug. 14
By Ed Sperling - 14 Aug, 2013 - Comments: 0

By Ed Sperling Synopsys’ Eric Huang unveils the fastest USB ever. The seat belt is extra. Mentor’s Nazita Saye sees the light—well, at least a refracted version of it—through the lens of a plastic bottle. This one is a real energy saver for the money, even if you have to forfeit the recycling fee. Check out the link. Cadence’s Brian Fuller takes a sledgehammer to the semicond... » read more

Hardware Accelerators Earn Their Keep
By Ann Mutschler - 08 Aug, 2013 - Comments: 0

By Ann Steffora Mutschler Hardware accelerators have been used for years, but with the proliferation of multicore chips and SoCs their use is evolving. Multicore processors have reduced the reliance on hardware accelerators, but that doesn’t mean the number of hardware accelerators is shrinking. The insatiable demand for performance while also reducing power consumption means that acceler... » read more

Experts At The Table: Low-Power Verification
By Ed Sperling - 08 Aug, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss power format changes with Sushma Hoonavera-Prasad, design engineer in Broadcom’s mobile platform group; John Biggs, consultant engineer for R&D and co-founder of ARM; Erich Marschner, product marketing manager at Mentor Graphics; Qi Wang, technical marketing group director at Cadence; and Jeffrey Lee, corporate app... » read more

How Secure Is Your SoC?
By Ed Sperling - 07 Aug, 2013 - Comments: 0

The Russian Federal Guard Service’s decision to revert to typewriters—machines that leave unique mechanical fingerprints—is a good indicator of just how serious security has become in a world dominated by electronics and pervasive connectivity. What’s less apparent is the growing threat at the SoC level—inside complex chips, between the chip and the board, and between chips on the ... » read more

The Rise Of Semiconductor IP Subsystems
By Various Writers - 06 Aug, 2013 - Comments: 0

The semiconductor IP (SIP) market arose when SIP vendors created IP functions that mirrored those found in the discrete semiconductor market and made those functions available to SoC designers in the form of hard or soft SIP blocks. As the SoC and SIP markets evolved, it was a natural evolution that many discrete SIP functions be converged into larger blocks that mimic system-level functions (i... » read more

Experts At The Table: Performance Analysis
By Ed Sperling - 02 Aug, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down with Ravi Kalyanaraman, senior verification manager for the digital entertainment business unit at Marvell; William Orme, strategic marketing manager for ARM’s System IP and Processor Division; Steve Brown, product marketing and business development director for the systems and software group at Cadence; Johannes Stahl director o... » read more

Next Phase Of Energy Efficiency Begins
By Ed Sperling - 02 Aug, 2013 - Comments: 0

Individual purchases and product rollouts by companies are difficult to assess by themselves. Sometimes they are isolated steps that have no context or connection to anything else—the proverbial toe-dipping exercise to see just how deep and cold the water is. Other times, they are the beginning of a huge market shift. In the mobile space—and increasingly in everything that mobile devices... » read more

Blog Review: July 31
By Ed Sperling - 31 Jul, 2013 - Comments: 0

By Ed Sperling Wherever you turn in IC design, there’s always someone talking about future problems involving the interconnect. Cadence’s Brian Fuller puts the latest speech by North Carolina State professor Paul Franzon in historical perspective—or at least in the shadow of the last dire prediction by Intel’s Mark Bohr two decades ago. Incidentally, Bohr’s warning turned out to be r... » read more

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