Week In Review: Auto, Security, Pervasive Computing


Automotive Ambarella will use Samsung's 5nm process technology for its new CV3-AD685 automotive AI central domain controller, bringing "new levels of AI acceleration, system integration and power efficiency to ADAS and L2+ through L4 autonomous vehicles.” Renesas introduced four technologies for automotive communication gateway SoCs: (1) an architecture that dynamically changes... » read more

Taming Corner Explosion In Complex Chips


There is a tenuous balance between the number of corners a design team must consider, the cost of analysis, and the margins they insert to deal with them, but that tradeoff is becoming a lot more difficult. If too many corners of a chip are explored, it might never see production. If not enough corners are explored, it could reduce yield. And if too much margin is added, the device may not be c... » read more

Leveraging Chip Data To Improve Productivity


The semiconductor ecosystem is scrambling to use data more effectively in order to increase the productivity of design teams, improve yield in the fab, and ultimately increase reliability of systems in the field. Data collection, analysis, and utilization is at the center of all these efforts and more. Data can be collected at every point in the design-through-manufacturing flow and into the f... » read more

Dealing With Performance Bottlenecks In SoCs


A surge in the amount of data that SoCs need to process is bogging down performance, and while the processors themselves can handle that influx, memory and communication bandwidth are straining. The question now is what can be done about it. The gap between memory and CPU bandwidth — the so-called memory wall — is well documented and definitely not a new problem. But it has not gone away... » read more

Beyond Human Reach: Meeting Design Targets Faster With AI-Driven Optimization


The implementation flow for semiconductor devices is all about optimizing for power, performance, area (PPA), or some combination of these attributes. The history of this flow in electronic design automation (EDA) tools is all about adding more automation, tightening iterative loops, and reducing the number of iterations. The goal is converging to the PPA targets faster while using fewer resour... » read more

Blog Review: Feb. 22


Siemens EDA's Harry Foster observes that the FPGA market continues to go through a similar complexity curve that the IC/ASIC market experienced in the early and mid-2000 timeframe. Synopsys' Mitch Heins explores the benefits of heterogeneous integration of lasers and active gain elements in a silicon-based photonic IC, including reduced system costs, size, weight, and power along with improv... » read more

Best Practices For Cybersecurity-Aware SoC Development With ISO 21434


The growth of electronics in cars is exposing a new vector for cyberattacks on owners and automotive companies’ reputations. The potential human cost of an attack on the car’s electronics is driving urgency in the adoption of cybersecurity-aware practices, from OEMs and Tier 1s to every component supplier in the automotive industry. The standard “ISO/SAE 21434:2021 Road vehicles — Cyber... » read more

Week In Review: Design, Low Power


It’s earnings season. Arm, Cadence, Synopsys, Siemens (consolidated), Rambus, and Renesas reported quarterly results over the past couple weeks. All posted year-over-year revenue growth, despite an overall challenging macroeconomic climate. A roundup of all the chip industry earnings reports from the past several weeks can be found here. The edge computing market is projected to jump to al... » read more

Managing Thermal-Induced Stress In Chips


At advanced nodes and in the most advanced packages, physics is no one's friend. Escalating density, smaller features, and thinner dies make it more difficult to dissipate heat, and they increase mechanical stress. On the flip side, thinner dielectrics and tighter spaces make it more difficult to insulate and protect against that heat, and in conjunction with those smaller features and higher d... » read more

Blog Review: Feb. 15


Siemens EDA's Harry Foster examines the relationship between verification maturity and non-trivial bug escapes into production, as well as whether safety critical development processes yield higher quality in terms of preventing bugs and achieving silicon success. Synopsys' Shankar Krishnamoorthy finds that the rapid progress of machine learning models is driving demand for more domain-speci... » read more

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