tag: system on chip

Reducing SoC Power With NoCs And Caches
By Andy Nightingale - 31 Oct, 2024 - Comments: 0

Today’s system-on-chip (SoC) designs face significant challenges with respect to managing and minimizing power consumption while maintaining high performance and scalability. Network-on-chip (NoC) interconnects coupled with innovative cache memories can address these competing requirements. Traditional NoCs SoCs consist of IP blocks that need to be connected. Early SoCs used bus-based archi... » read more

Overview Of Security Verification Methodologies for SoC Designs Pre-Silicon (U. of Florida)
By Technical Paper Link - 23 Oct, 2024 - Comments: 0

A technical paper titled "A Survey on SoC Security Verification Methods at the Pre-silicon Stage" was recently published by researchers at University of Florida. Abstract "This paper presents a survey of the state-of-the-art pre-silicon security verification techniques for System-on-Chip (SoC) designs, focusing on ensuring that designs, implemented in hardware description languages (HDLs) a... » read more

Making Cache Coherent SoC Design Easier with Ncore
By Arteris - 28 Aug, 2024 - Comments: 0

As the number and variety of computing elements in SoCs grow, specific application areas require the tight connection of key processing elements through coherency. Ncore Interconnect IP from Arteris makes cache coherent SoC designs easier, saving 100’s of person-years effort per project vs DIY solutions. This white paper discusses the challenges and solutions in designing cache-coherent Sy... » read more

Why SoC Designers Need Purpose-Built Semiconductor IP Catalog Tools
By Roberto Piacentini Filho - 25 Jul, 2024 - Comments: 0

Semiconductor intellectual property (IP) management, reuse, and change tracking are essential for efficiently creating chip designs based on proven building blocks, reducing your time-to-market, and maintaining good reputations throughout their lifetimes. Unfortunately, many SoC teams attempt to use existing tools like Git for these essential tasks, even though they are unsuitable and inconv... » read more

Resilient And Secure Programmable SoC Accelerator Offload (KAUST)
By Technical Paper Link - 03 Jul, 2024 - Comments: 0

A technical paper titled “Resilient and Secure Programmable System-on-Chip Accelerator Offload” was published by researchers at King Abdullah University of Science and Technology (KAUST). Abstract: "Computational offload to hardware accelerators is gaining traction due to increasing computational demands and efficiency challenges. Programmable hardware, like FPGAs, offers a promising plat... » read more

Competitive Open-Source EDA Tools
By Technical Paper Link - 19 May, 2024 - Comments: 0

A technical paper titled “Basilisk: Achieving Competitive Performance with Open EDA Tools on an Open-Source Linux-Capable RISC-V SoC” was published by researchers at ETH Zurich and University of Bologna. Abstract: "We introduce Basilisk, an optimized application-specific integrated circuit (ASIC) implementation and design flow building on the end-to-end open-source Iguana system-on-chip (... » read more

Modeling And Analyzing Open-Source SoCs For Low-Power Cyber-Physical Systems
By Technical Paper Link - 08 Feb, 2024 - Comments: 0

A technical paper titled “TOP: Towards Open & Predictable Heterogeneous SoCs” was published by researchers at University of Bologna, ETH Zurich, and University of California San Diego. Abstract: "Ensuring predictability in modern real-time Systems-on-Chip (SoCs) is an increasingly critical concern for many application domains such as automotive, robotics, and industrial automation. An... » read more

SoC Integration And Data Transport Architecture Requirements Surge In 2023
By Frank Schirrmeister - 30 Nov, 2023 - Comments: 0

As the holiday season is in full swing, it's retrospection and prediction time! Let's look at what I thought 2023 would look like, review how it turned out, and take a first stab at 2024 predictions. As a spoiler, my biggest surprise was the intensity with which artificial intelligence and machine learning (AI/ML) accelerated since Generative AI was put on the mainstream adoption map last year,... » read more

A HIL Methodology For The SoC Development Flow
By Technical Paper Link - 14 Nov, 2023 - Comments: 0

A technical paper titled “Virtual-Peripheral-in-the-Loop : A Hardware-in-the-Loop Strategy to Bridge the VP/RTL Design-Gap” was published by researchers at University of Bremen and German Research Center for Artificial Intelligence (DFKI). Abstract: "Virtual Prototypes act as an executable specification model, offering a unified behavior reference model for SW and HW engineers. However, b... » read more

A Formal Verification Method To Detect Timing Side Channels In MCU SoCs
By Technical Paper Link - 11 Oct, 2023 - Comments: 0

A technical paper titled “A New Security Threat in MCUs – SoC-wide timing side channels and how to find them” was published by researchers at University of Kaiserslautern-Landau and Stanford University. Abstract: "Microarchitectural timing side channels have been thoroughly investigated as a security threat in hardware designs featuring shared buffers (e.g., caches) and/or parallelism b... » read more

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