Chip Industry’s Technical Paper Roundup: October 24


New technical papers added to Semiconductor Engineering’s library this week. [table id=157 /] More Reading Technical Paper Library home » read more

FeFET Multi-Level Cells For In-Memory Computing In 28nm


A technical paper titled “First demonstration of in-memory computing crossbar using multi-level Cell FeFET” was published by researchers at Robert Bosch, University of Stuttgart, Indian Institute of Technology Kanpur, Fraunhofer IPMS, RPTU Kaiserslautern-Landau, and Technical University of Munich. Abstract: "Advancements in AI led to the emergence of in-memory-computing architectures as a... » read more

Chip Industry’s Technical Paper Roundup: October 3


New technical papers recently added to Semiconductor Engineering’s library: [table id=150 /] Related Reading Technical Paper Library home » read more

SRAM-Based IMC For Cryogenic CMOS Using Commercial 5 nm FinFETs


A technical paper titled “Cryogenic In-Memory Computing for Quantum Processors Using Commercial 5-nm FinFETs” was published by researchers at University of Stuttgart, Indian Institute of Technology Kanpur, University of California Berkeley, and Technical University of Munich. Abstract: "Cryogenic CMOS circuits that efficiently connect the classical domain with the quantum world are the co... » read more

The Race Toward Quantum Advantage


Quantum computing has yet to show an advantage over conventional computing, but huge sums of money are betting it will. So far that hasn't happened. Early quantum computers were created in the mid-1990s after mathematicians had demonstrated the effectiveness of applying quantum approaches to some problems. At that stage they were simulated using conventional computing, but it started the rac... » read more

Quantum Research Bits: Sept. 12


Making Qubits Last Longer One of the big challenges in quantum computing is extending the lifespan of qubits, called coherence time, long enough to do something useful with them. Research is now focused on how to increase that usable lifetime, and what factors can impact that. This has led to very different conclusions about whether silicon is a good substrate choice for quantum chips. Rese... » read more

Research Bits: Aug. 30


Through glass vias Researchers from the Chinese Academy of Sciences (CAS) developed a Through Glass Via (TGV) process for 3D advanced packaging, which they say enables low transmission loss and high vacuum wafer-level packaging of high-frequency chips and MEMS sensors. TGV is a vertical interconnection technology applied in wafer-level vacuum packaging. The researchers found that it has goo... » read more

Technical Paper Roundup: Aug. 30


New technical papers added to Semiconductor Engineering’s library this week. [table id=47 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit for... » read more

Training a Quantum Neural Network Requires Only A Small Amount of Data


A new research paper titled "Generalization in quantum machine learning from few training data" was published by researchers at Technical University of Munich, Munich Center for Quantum Science and Technology (MCQST), Caltech, and Los Alamos National Lab. “Many people believe that quantum machine learning will require a lot of data. We have rigorously shown that for many relevant problems,... » read more

Technical Paper Round-Up: March 22


New memories, materials, and transistor types, and processes for making those devices, highlighted the past week's technical papers. That includes everything from vertical MoS2 to programmable black phosphorus image sensors and photonic lift-off processes for flexible thin-film materials. Papers continue to flow from all parts of the supply chain, with some new studies out of Pakistan, Seoul... » read more

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