tag: test

Testing Cars In Context
By Ed Sperling - 12 Jul, 2018 - Comments: 0

The choices for companies developing systems or components that will work in autonomous vehicles is to road test them for millions of miles or to simulate them, or some combination of both. Simulation is much quicker, and it has worked well in the semiconductor world for decades. Simulating a chip or electronic system in context is hard enough. But simulating a system of systems in the real... » read more

Preparing For A 5G World
By Ed Sperling - 12 Jul, 2018 - Comments: 0

Semiconductor Engineering sat down to talk about challenges and progress in 5G with Yorgos Koutsoyannopoulos, president and CEO of Helic; Mike Fitton, senior director of strategic planning and business development at Achronix; Sarah Yost, senior product marketing manager at National Instruments; and Arvind Vel, director of product management at ANSYS. What follows are excerpts of that conversat... » read more

Security Holes In Machine Learning And AI
By Ed Sperling - 09 Jul, 2018 - Comments: 0

Machine learning and AI developers are starting to examine the integrity of training data, which in some cases will be used to train millions or even billions of devices. But this is the beginning of what will become a mammoth effort, because today no one is quite sure how that training data can be corrupted, or what to do about it if it is corrupted. Machine learning, deep learning and arti... » read more

Improving Test Coverage And Eliminating Test Escapes Using Analog Defect Analysis
By Cadence - 13 Jun, 2018 - Comments: 0

While the analog and mixed-signal components are the leading source of test escapes that result in field failures, the lack of tools to analyze the test coverage during design has made it difficult for designers to address the issue. In this white paper, we explore the methodology for performing analog fault simulation of test coverage based on defect-oriented testing. In addition, we look at h... » read more

Putting “Design” Back Into Design For Test In PCB Products
By Mentor, a Siemens Business - 11 Jun, 2018 - Comments: 0

Design for manufacturing (DFM) has become a proactive part of the design process, but the same cannot be said for DFT. Whereas “left-shifting” DFM has reduced manufacturing problems, increased yield, reduced scrap levels, and simplified engineering rework, testability-related improvements have stayed flat during that same time. Unfortunately, as assembly costs have come down, and test-relat... » read more

Software-Defined Test And Measurement
By Jeff Dorsch - 07 May, 2018 - Comments: 0

Software-defined radios, instrumentation and test are ramping up alongside a flood of new technologies related to assisted and autonomous vehicles, 5G, and military/aerospace electronics, breathing new life and significant change into the test and measurement market. Software-defined test adds flexibility in markets where the products and protocols are evolving or still being defined, and wh... » read more

How Automotive ICs Are Reshaping Semiconductor Test
By Steve Pateras - 22 Mar, 2018 - Comments: 0

The growth of a new IC market creates ripples along the entire supply chain. Today, we see the semiconductor industry reacting to the needs of the growing automotive IC market, including the development of new IC test tools and methods. The automotive IC market is far and away the fastest growing end-use market with 15% CAGR (according to IC Insights). It is also seeing many new players. Mar... » read more

Tech Talk: Faster Simulation
By Ann Mutschler - 22 Mar, 2018 - Comments: 0

Cadence’s Adam Sherer talks about how to speed up simulation in complex multi-core designs. https://youtu.be/lDgMwU5KN7U » read more

DO-254: Increasing Verification Coverage By Test
By Aldec - 21 Mar, 2018 - Comments: 0

Verification coverage by test is essential to satisfying both the objectives of DO-254 and interpretation in FAA Oder 8110.105. However, verification of requirements by test during final board testing is challenging and time-consuming in most cases. This white paper explains the reasons behind these challenges and provides recommendations for how to overcome them. The recommendations center ... » read more

What’s In The Package?
By Ed Sperling - 05 Feb, 2018 - Comments: 0

Putting a variety of chips or hardened IP blocks into a package rather than trying to cram them into a single chip continues to gain ground. But it's also creating its own set of issues around verifying and testing these devices. This problem is well understood inside of SoCs, where everything is integrated into a single die. And looked at from a 30,000-foot perspective, packaging is someth... » read more

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