tag: test

Interpreting UPF For A Mixed-Signal Design Under Test
By Mentor, a Siemens Business - 23 Jul, 2014 - Comments: 0

This paper describes a methodology (as implemented in the Mentor Graphics Questa ADMS mixed-signal simulator) for interpreting the Unified Power Format (UPF) for analog mixed-signal designs coded in Verilog-AMS, VHDL-AMS, or SPICE. No changes to the UPF syntax or file are required. A complete implementation and a demonstration of its use in a sample case are provided as proof of concept. To ... » read more

More Effective Test: Slack-Based Transition Delay
By Synopsys - 23 Jul, 2014 - Comments: 0

Semiconductor companies have come to rely on delay testing to attain high defect coverage of manufactured digital integrated circuits (ICs). Delay testing uses transition delay (TD) patterns created by automatic test pattern generation (ATPG) tools to target subtle manufacturing defects in fabricated designs. Although standard TD testing improves defect coverage beyond levels stuck-at patterns ... » read more

Designing And Testing FinFET-based IC Designs
By Mentor Graphics Staff Writers - 19 Jun, 2014 - Comments: 0

By Carey Robertson and Steve Pateras The emergence of FinFET transistors has had a significant impact on the IC physical design and design-for-test flows. The introduction of FinFETs means that CMOS transistors must be modeled as three-dimensional (3D) devices during the IC design process, with all the complexity and uncertainty this entails. The BSIM Group of the UC Berkeley Device Group has ... » read more

Five Disruptive Test Technologies
By Mark LaPedus - 19 Jun, 2014 - Comments: 0

For years, test has been a critical part of the IC manufacturing flow. Chipmakers, OSATs and the test houses buy the latest testers and design-for-test (DFT) software tools in the market and for good reason. A plethora of unwanted field returns is not acceptable in today’s market. The next wave of complex chips may require more test coverage and test times. That could translate into higher... » read more

SEMICON West Preview: Test
By Paula Doe - 19 Jun, 2014 - Comments: 0

Talking with the speakers scheduled to speak in the programs on IC testing at SEMICON West this year, I was struck by how much this equipment sector is changing as the value moves to software and the cloud. It has to be the first time I’ve ever mentioned PayPal in the same paragraph with semiconductor equipment, to say nothing of the business model of free hardware with software subscription.... » read more

Tech Talk: Concurrent Test
By Ed Sperling - 18 Jun, 2014 - Comments: 2

Dave Armstrong, director of business development at Advantest, discusses the usefulness of concurrent test and describes how to maximize the value of this approach. [youtube vid=UFPxTlB2LWQ] » read more

Semicon West Preview: Packaging
By SEMI - 09 Jun, 2014 - Comments: 0

By Paula Doe The evolving mobile device market means the packaging, assembly and test supply chain faces a growing range of alternative technologies vying for its investment dollar, everything from Google’s modular electronics with 3D printing, to more solutions for integrating varied chips in smaller packaged systems. One potentially disruptive change is the wider use of more open-source... » read more

Test Challenges Grow
By Mark LaPedus - 27 May, 2014 - Comments: 3

Semiconductor Engineering sat down to discuss current and future test challenges with Dave Armstrong, director of business development at Advantest; Steve Pateras, product marketing director for Silicon Test Solutions at Mentor Graphics; Robert Ruiz, senior product marketing manager at Synopsys; Mike Slessor, president of FormFactor; and Dan Glotter, chief executive of Optimal+. SE: In our ... » read more

The Circle Of Test And EDA Is Complete
By Brian Bailey - 22 May, 2014 - Comments: 1

For those of you who were around and involved with EDA back in the early ’80s, you may remember that chip design was not the focus. It was the board that received most of the attention. Chips were small and did not require much in the way of functional verification. [getkc id="29" kc_name="Synthesis"] had not been invented and so gate-level design was where everything happened, and much of th... » read more

How Much Testing Is Enough?
By Mark LaPedus - 15 May, 2014 - Comments: 1

As chipmakers move towards finer geometries, IC designs are obviously becoming more complex and expensive. Given the enormous risks involved, chipmakers must ensure the quality of the parts before they go out the door. And as part of quality assurance process, that requires a sound test strategy. But for years, IC makers have faced the same dilemma. On one hand, they want a stringent test me... » read more

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