Application and Verification of Effective Heat Spreading Angles on a Multi-Layer Thermal Design


Abstract: "When designing converters, the average junction temperature of the semiconductor is a frequently required estimate. Its analytical calculation requires the total thermal resistance of the cooling arrangement. Unfortunately, due to the complexity of the heat dissipation processes, an estimate of the thermal resistance is usually associated with low accuracy. To significantly improve ... » read more

Energy-Efficient SoCs For The Zettabyte Era Using Power-Saving IP And System Design Techniques


As the modern world becomes increasingly connected, businesses and consumers alike are relying more and more on digital data. Behind the scenes, data centers that manage all of this digital data are a somewhat silent, yet impactful, part of this connectivity revolution. These data centers are lined with servers that process digital data for everything from social media status updates to analyti... » read more

Building Complex Chips That Last Longer


Semiconductor Engineering sat down to talk about design challenges in advanced packages and nodes with John Lee, vice president and general manager for semiconductors at Ansys; Shankar Krishnamoorthy, general manager of Synopsys' Design Group; Simon Burke, distinguished engineer at Xilinx; and Andrew Kahng, professor of CSE and ECE at UC San Diego. This discussion was held at the Ansys IDEAS co... » read more

Thermal And Stress Analysis Of 3D-ICs With Celsius Thermal Solver


As electronics get smaller and faster, the environment for thermal issues is becoming more and more challenging. These problems are widespread and can appear in the chip, the board, the package, and the entire system. This white paper helps designers understand the cross-fabric thermal and stress challenges introduced by 3D-ICs and how the Cadence Celsius  Thermal Solver helps designers analyz... » read more

Best 112G SerDes IP Architecture


Real world operation of a serializer/deserializer (SerDes) in a hyperscale data center is very demanding and requires robust performance in challenging conditions such as multitude of channel insertion loss, extreme temperature cycles, different types of packages with different trace lengths and discontinuities, etc. Hence, meeting interference tolerance (ITOL) and jitter tolerance (JTOL) compl... » read more

Shifting Left: Early Multi Physics Analysis For STCO


With the economics of transistor scaling no longer universally applicable, the industry is turning to innovative packaging technologies to support system scaling demands and achieve lower system cost. This has led to the emergence of a system technology co-optimization (STCO) approach, in which an SoC is disaggregated into smaller modules (also known as chiplets) that can be asynchronously desi... » read more

High Thermal Die-Attach Paste Development For Analog Circuits


In recent years, various die attach (DA) materials have been developed to cope with the higher power dissipation requirements of semiconductor devices. DA materials based on metals such as solder or sintered silver (Ag) are used for very high heat generating power devices. While they show outstanding thermal performance, the mechanical properties of these materials are less than ideal. This lim... » read more

Thermal Floorplanning For Chips


Heat management is becoming crucial to an increasing number of chips, and it's one of a growing number of interconnected factors that must be considered throughout the entire development flow. At the same time, design requirements are exacerbating thermal problems. Those designs either have to increase margins or become more intelligent about the way heat is generated, distributed, and dissi... » read more

Mapping Heat Across A System


Thermal issues are becoming more difficult to resolve as chip features get smaller and systems get faster and more complex. They now require the integration of technologies from both the design and manufacturing flows, making design for power and heat a much broader problem. This is evident with the evolution of a smart phone. Phones sold 10 years ago were very different devices. Functionali... » read more

How Heterogeneous ICs Are Reshaping Design Teams


Experts at the Table: Semiconductor Engineering sat down to discuss the complex interactions developing between different engineering groups as designs become more heterogeneous, with Jean-Marie Brunet, senior director for the Emulation Division at Siemens EDA; Frank Schirrmeister, senior group director for solution marketing at Cadence; Maurizio Griva, R&D Manager at Reply; and Laurent Mai... » read more

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