tag: thermal

Power/Performance Bits: April 14
By Jesse Allen - 14 Apr, 2020 - Comments: 0

Undoped polymer ink Researchers at Linköping University, Chalmers University of Technology, University of Washington, University of Cologne, Chiba University, and Yunnan University developed an organic ink for printable electronics that doesn't need to be doped for good conductivity. "We normally dope our organic polymers to improve their conductivity and the device performance. The proces... » read more

Using Digital Image Correlation To Determine BGA Warpage
By Craig Hillman - 16 Jan, 2020 - Comments: 0

Digital image correlation (DIC) is a non-contact, full-field displacement, optical measurement technique. It is often used in the following applications: Material characterization Coefficient of thermal expansion (CTE) Glass transition temperature Young’s modulus Poisson’s ratio Sample testing for fatigue and failure In situ monitoring of displacements and str... » read more

Analog: Avoid Or Embrace?
By Brian Bailey - 16 Jan, 2020 - Comments: 0

We live in an analog world, but digital processing has proven quicker, cheaper and easier. Moving digital data around is only possible while the physics of wires can be safely abstracted away enough to provide reliable communications. As soon as a signal passes off-chip, the analog domain reasserts control for modern systems. Each of those transitions requires a data converter. The usage ... » read more

Power/Performance Bits: Jan. 7
By Jesse Allen - 07 Jan, 2020 - Comments: 0

Ferroelectric FET Researchers at Purdue University developed a ferroelectric transistor capable of both processing and storing information. The ferroelectric semiconductor field-effect transistor is made of alpha indium selenide, which overcomes the problem of ferroelectric materials not interfacing well with silicon. “We used a semiconductor that has ferroelectric properties. This way tw... » read more

Thermal Challenges In Advanced Packaging
By Ed Sperling - 02 Dec, 2019 - Comments: 2

CT Kao, product management director at Cadence, talks with Semiconductor Engineering about why packaging is so complicated, why power and heat vary with different use cases and over time, and why a realistic power map is essential particularly for AI chips, where some circuits are always on.   Interested in more Semiconductor Engineering videos? Sign-up for our YouTube channel here » read more

Finding Hotspots In AI Chips
By Stephen Crosher - 14 Nov, 2019 - Comments: 0

Things are getting far more complicated as we move down to 7nm & 5nm but the tolerances of some of the physical effects that we have been measuring in the past are much tighter than they were at the older nodes. How do we track all that? What we see is that as we descend through the advanced nodes, say from 16nm down to 12nm, 7nm and more recently 5nm, we see that gate density starts to ... » read more

Thermal Challenges And Moore’s Law
By Ed Sperling - 22 Oct, 2019 - Comments: 0

Steven Woo, fellow and distinguished inventor at Rambus, looks at the evolution of graphics cards over a couple of decades and how designs changed to deal with more graphics and more heat, and why smaller, faster and cheaper doesn’t apply in this market. » read more

Monitoring Heat On AI Chips
By Ed Sperling - 11 Oct, 2019 - Comments: 0

Stephen Crosher, CEO of Moortec, talks about monitoring temperature differences on-chip in AI chips and how to make the most of the power that can be delivered to a device and why accuracy is so critical. » read more

Less Margin, More Respins, And New Markets
By Ed Sperling - 10 Oct, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss the impact of multi-physics and new market applications on chip design with John Lee, general manager and vice president of ANSYS' Semiconductor Business Unit; Simon Burke, distinguished engineer at Xilinx; Duane Boning, professor of electrical engineering and computer science at MIT; and Thomas Harms, director EDA/IP Alliance at Infineon. What foll... » read more

Another Brick Or Two In The Chip Design Wall
By Ed Sperling - 12 Sep, 2019 - Comments: 1

Physical challenges come and go in the semiconductor world. But increasingly, they also stick around, showing up in inconvenient places at the worst time. The chip industry has confronted and solved some massive challenges over the years. There was the 1 micron lithography wall, which was supposed to be impenetrable. That was followed by the 193nm litho challenge, which cost many billions of... » read more

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