tag: through-silicon vias

Time To Revisit 2.5D And 3D
By Mark LaPedus - 17 Apr, 2014 - Comments: 2

Chipmakers are reaching various and challenging inflection points. In logic, many IC makers face a daunting transition from planar transistors at 20nm to finFETs at 14nm. And on another front, the industry is nearing the memory bandwidth wall. So perhaps it’s time to look at new alternatives. In fact, chipmakers are taking a hard look, or re-examining, one alternative—stacked 2.5D/3D chi... » read more

Many Stresses Impact TSVs
By Ann Mutschler - 20 Feb, 2014 - Comments: 0

Too much stress in humans is typically not beneficial, and the same goes for 3D-ICs with through-silicon vias (TSVs). Stress effects here come from the fact that copper, which is the conductor of choice for the TSVs, and silicon have different coefficients of thermal expansion. “If you can imagine that a via will be etched through the silicon, copper will be deposited inside and then t... » read more

Manufacturing Bits: Jan. 21
By Mark LaPedus - 21 Jan, 2014 - Comments: 1

Redefining The Kilogram In 2011, the General Conference on Weights and Measures approved a plan to redefine the kilogram and other measurement units. The new definition for the kilogram will be based on the fixed numerical values of Planck’s constant (h), according to the National Institute of Standards and Technology (NIST), part of the U.S. Department of Commerce. NIST has taken steps t... » read more

The Upside Of Through-Silicon Vias
By Katherine Derbyshire - 17 Oct, 2013 - Comments: 0

Through-silicon vias (TSVs) for 3D integration are superficially similar to damascene copper interconnects for integrated circuits. Both etch the via, into either silicon or a dielectric, line it with a barrier against copper diffusion, then deposit a seed layer prior to filling the via with copper using some form of aqueous deposition. In both processes, the integrity of the diffusion barrier ... » read more

Bigger Pipes, New Priorities
By Ed Sperling - 28 Jul, 2011 - Comments: 0

By Ann Steffora Mutschler From the impact of stacking on memory subsystems to advances in computing architecture, Micron Technology is at the forefront in the memory industry. System-Level Design sat down to discuss challenges, as well as some possible solutions, that plague memory subsystem architects with Scott Graham, general manager for Micron’s Hybrid Memory Cube (HMC) and Joe Jeddeloh,... » read more

Preparing For 3D IC Stacking
By Ed Sperling - 22 Jul, 2010 - Comments: 0

By David Lammers Through-silicon vias (TSVs) are in various stages of late development, but design and manufacturing challenges remain before companies can gain the full benefits of the third dimension. Two camps are pushing hard to introduce TSVs—the design community and the manufacturing equipment companies. The initial goal is to connect graphics memories to graphics processors in mobi... » read more

Stressing Over 3D
By Ed Sperling - 24 Jun, 2010 - Comments: 0

By David Lammers Pol Marchal recalls putting a stacked 3D prototype on his desk at IMEC in Leuven, Belgium, last year, which a visitor picked up and examined two months later. “I don’t think this chip will work,” the visitor said, causing Marchal, principal scientist at IMEC’s 3D system integration program, to put the stacked die under a microscope. Sure enough, Pol found that mechanic... » read more

3D Integration: Extending Moore’s Law Into The Next Decade
By Cheryl Ajluni - 27 Aug, 2009 - Comments: 0

By Cheryl Ajluni At the 46th Design Automation Conference in San Francisco last month, attention turned to a discussion of how to extend the momentum of Moore’s Law into the next decade. One plausible solution, according to Philippe Magarshack, the general manager of Central CAD & Design Solutions at STMicroelectronics, is 3D stacking for complex System-on-Chips (SoCs). The concept of 3... » read more

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