Automated Late Stage Timing-Aware Dynamic Voltage Drop ECO

By Manoj Chacko - 09 Jan, 2023 - Comments: 0

One of the never-ending frustrations for electrical engineers is having to deal with counterproductive real-world effects that they wish would just go away. Examples include switch bounce, metastability, and contact resistance. For IC designers, dynamic voltage drop (DVD), also known as IR drop, is one of those unfortunate facts of the profession. There’s no way to avoid it; every trace and w... » read more

On-Chip Power Distribution Modeling Becomes Essential Below 7nm

By Ann Mutschler - 16 Nov, 2022 - Comments: 0

Modeling power distribution in SoCs is becoming increasingly important at each new node and in 3D-ICs, where tolerances involving power are much tighter and any mistake can cause functional failures. At mature nodes, where there is more metal, power problems continue to be rare. But at advanced nodes, where chips are running at higher frequencies and still consuming the same or greater power... » read more

Closing The Post-Silicon Timing Analysis Gap

By Ash Patel - 10 May, 2022 - Comments: 0

Accurate static timing analysis is one of the most important steps in the development of advanced node semiconductor devices. Performance numbers are included in chip and system specifications from the earliest marketing requirements. The architects and designers carefully determine clock cycle times that can achieve the required performance using the chosen high-level architecture, micro-archi... » read more

Timing Challenges In The Age Of AI Hardware

By Quiyang Wu - 25 Feb, 2021 - Comments: 0

In recent years, we have seen a clear market trend towards dedicated integrated circuits (ASICs) that are much more efficient in performance and energy consumption than traditional general-purpose computers for processing AI workloads. These AI accelerators harden deep learning algorithm kernels into circuits, enable higher data ingestion bandwidth with local memory, and perform massively paral... » read more

Thermal Impact On Reliability At 7/5nm

By Ed Sperling - 28 Sep, 2018 - Comments: 0

Haroon Chaudhri, director of RedHawk Analysis Fusion at Synopsys, talks about why thermal analysis is shifting left in the design cycle and why this is so critical at the most advanced process nodes. https://youtu.be/wjkrEFLb2vY » read more

Hierarchical Timing Analysis: Pros, Cons, And A New Approach

By Various Writers - 23 Apr, 2014 - Comments: 0

As digital semiconductor designs continue to grow larger, designers are looking to hierarchical methodologies to help alleviate huge runtimes. This approach allows designers to select and time certain blocks of logic, generating results more quickly and with fewer memory resources. However, these benefits come at the cost of accuracy. This paper covers the pros and cons of different hierarchica... » read more

Timing Bomb

By Ed Sperling - 22 Apr, 2010 - Comments: 0

By Ed Sperling Timing closure, a basic operation in chip design and development, is becoming anything but basic at advanced process nodes. Systematic variability that was at least predictable at 90nm has become random at 45nm. Tools that worked fine with two corner cases now have to deal with hundreds. And as more functions make their way onto a single die, often with multiple modes of oper... » read more

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Entities, people and technologies explored

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: timing analysis

Automated Late Stage Timing-Aware Dynamic Voltage Drop ECO

On-Chip Power Distribution Modeling Becomes Essential Below 7nm

Closing The Post-Silicon Timing Analysis Gap

Timing Challenges In The Age Of AI Hardware

Thermal Impact On Reliability At 7/5nm

Hierarchical Timing Analysis: Pros, Cons, And A New Approach

Timing Bomb

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