tag: timing

Low-Power IC Design Without Compromise
By Janet Attar - 09 Mar, 2023 - Comments: 0

In the process of creating ICs, the digital implementation stage is focused on meeting the performance, power, and area (PPA) targets defined for the design. Traditionally, when talking about PPA metrics, “performance” has been the primary focus, with power and area recovered where possible, after meeting timing. But as designs have moved to smaller, more advanced process nodes, and as s... » read more

Optimizing Vmin With Path Margin Monitors
By Ash Patel - 24 Oct, 2022 - Comments: 0

By Firooz Massoudi and Ash Patel Choosing the right operating voltage for various digital blocks within a semiconductor device is one of the most important tasks faced by chip designers. Operating voltage has major effects on performance, power consumption, and reliability. Increasing the voltage generally increases performance, but at the cost of more power and higher lifetime operating cos... » read more

ECO Should Not Stand For Extended Challenge Order
By Manoj Chacko - 25 Aug, 2022 - Comments: 0

There’s an old saying that the first 90% of a task takes 90% of the schedule, and the remaining 10% takes the other 90% of the time. In chip development, design-signoff closure has become one such task. Ideally, when the design has been placed and routed (physical implementation), final analysis of timing and other metrics is performed and an engineering change order (ECO) file is issued to t... » read more

Cutting Clock Costs On The Bleeding Edge Of Process Nodes
By Aakash Jani - 01 Aug, 2022 - Comments: 0

In a recent study done by McKinsey and IDC, we see that physical design and verification costs are increasing exponentially with shrinking transistor sizes. As figure 1 shows, physical design (PD) and pre-silicon verification costs are doubling each process leap. As companies leap from node to leading node, a natural question arises. Why is it becoming harder and more expensive to tapeout a chi... » read more

Enabling Big Chip AI Solutions Through Intelligent Clock Networks
By Aakash Jani - 26 May, 2022 - Comments: 0

Data centers, autonomous vehicles, and computer vision applications are pushing the limits of scalable AI compute. Data center chips face multi-trillion parameter models that continue growing every year. ADAS systems require flexibility and processing power for new model types, such as vision transformers. Edge AI solutions demand tight power budgets and the ability to process multiple models i... » read more

Preparing For 3D-ICs
By Ed Sperling - 16 Feb, 2022 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss the changes in design tools and methodologies needed for 3D-ICs, with Sooyong Kim, director and product specialist for 3D-IC at Ansys; Kenneth Larsen, product marketing director at Synopsys; Tony Mastroianni, advanced packaging solutions director at Siemens EDA; and Vinay Patwardhan, product management group director at Cadence... » read more

Power Optimization: What’s Next?
By Brian Bailey - 17 May, 2021 - Comments: 2

Concerns about the power consumed by semiconductors has been on the rise for the past couple of decades, but what can we expect to see coming in terms of analysis and automation from EDA companies, and is the industry ready to make the investment? Ever since Dennard scaling stopped providing automatic power gains by going to a smaller geometry, circa 2006, semiconductors have been increasing... » read more

Timing Challenges In The Age Of AI Hardware
By Quiyang Wu - 25 Feb, 2021 - Comments: 0

In recent years, we have seen a clear market trend towards dedicated integrated circuits (ASICs) that are much more efficient in performance and energy consumption than traditional general-purpose computers for processing AI workloads. These AI accelerators harden deep learning algorithm kernels into circuits, enable higher data ingestion bandwidth with local memory, and perform massively paral... » read more

Taming Non-Predictable Systems
By Brian Bailey - 28 Jan, 2021 - Comments: 0

How predictable are semiconductor systems? The industry aims to create predictable systems and yet when a carrot is dangled, offering the possibility of faster, cheaper, or some other gain, decision makers invariably decide that some degree of uncertainty is warranted. Understanding uncertainty is at least the first step to making informed decisions, but new tooling is required to assess the im... » read more

Lower Process Nodes Drive Timing Signoff Software Evolution
By Synopsys - 10 Nov, 2020 - Comments: 0

A dramatic rise in design complexity has led to a slew of new signoff challenges that impact the ability to predictably meet PPA targets. Smaller technology nodes and larger design sizes have caused the number of corners and modes to grow exponentially leading to much longer turnaround times for timing signoff. Moreover, larger design sizes demand huge compute resources for timing signoff. I... » read more

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