tag: Tortuga Logic

Verifying Security In Processor-based SoCs
By Ruud Derwig - 12 Dec, 2019 - Comments: 0

By Ruud Derwig and Nicole Fern Security in modern systems is of utmost importance. Device manufacturers are including multiple security features and attack protections into both the hardware and software design. For example, the Synopsys DesignWare ARC Processor IP includes many security functions in its SecureShield feature set. End-product system security, however, cannot be guaranteed by ... » read more

New Security Risks Create Need For Stealthy Chips
By Ed Sperling - 03 Oct, 2019 - Comments: 0

Semiconductors are becoming more vulnerable to attacks at each new process node due to thinner materials used to make these devices, as well as advances in equipment used to simulate how those chips behave. Thinner chips are now emitting light, electromagnetic radiation and various other types of noise, which can be observed using infrared and acoustic sensors. In addition, more powerful too... » read more

A Complete System-Level Security Verification Methodology
By Cadence - 04 Sep, 2019 - Comments: 0

Hardware is at the root of all digital systems, and security must be considered during the system-on-chip (SoC) design and verification process. Verifying the security of an SoC design is challenging because of time to market pressure and resource constraints. Resources allocated to the already time-consuming task of functional verification must be diverted to security verification, which requi... » read more

Week In Review: Design, Low Power
By Jesse Allen - 16 Aug, 2019 - Comments: 0

Everspin and Seagate inked a patent cross-licensing agreement, including the assignment and licensing of MRAM patents from Seagate to Everspin as well as licensing of specific Tunneling Magnetoresistance (TMR) patents from Everspin to Seagate, which will be used in HDD read/write head technology. Subaru utilized ANSYS' SCADE suite for critical control systems to design and validate embedded ... » read more

Security’s Very Strange Path To Success
By Ed Sperling - 02 Jul, 2019 - Comments: 0

Security at the chip level appears to be heading toward a more promising future. The reason is simple—more people are willing to pay for security than in the past. For the most part, security is like insurance. You don't know it's working until something goes wrong, and you don't necessarily even know right away if there has been a breach. Sometimes it takes years to show up, because it ca... » read more

Who’s Responsible For Security Breaches?
By Brian Bailey - 24 Jun, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss industry attitudes towards safety and security with Dave Kelf, chief marketing officer for Breker Verification; Jacob Wiltgen, solutions architect for functional safety at Mentor, a Siemens Business; David Landoll, solutions architect for OneSpin Solutions; Dennis Ciplickas, vice president of characterization solutions at PDF Solutions; Andrew Dauma... » read more

Hacking SoC IP Under Pressure
By Susan Rambo - 11 Jun, 2019 - Comments: 0

Hack@DAC certainly shows that some teams can find bugs faster than others. The hackfest, now in its third year, is a bug-finding contest for teams of university students joined by a smattering of industry members whose task is to find a bugs implanted in SoC IP.  The teams follow the practices of real-world security teams. “[The teams'] objective is to identify the security vulnerabilitie... » read more

Disregard Safety And Security At Your Own Peril
By Brian Bailey - 10 Jun, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss industry attitudes towards safety and security with Dave Kelf, chief marketing officer for Breker Verification; Jacob Wiltgen, solutions architect for functional safety at Mentor, a Siemens Business; David Landoll, solutions architect for OneSpin Solutions; Dennis Ciplickas, vice president of characterization solutions at PDF Solutions; Andrew Dauma... » read more

Week In Review: Design, Low Power
By Jesse Allen - 26 Apr, 2019 - Comments: 0

A new working group has been proposed by Accellera to focus on the standardization of analog/mixed signal extensions (AMS) for the Universal Verification Methodology (UVM) standard. “Our ambition is to apply UVM for both digital and analog/mixed-signal verification,” said Martin Barnasconi, Accellera Technical Committee Chair. “The UVM-AMS PWG will assess the benefits of creating analog a... » read more

Next Wave Of Security For IIoT
By Kevin Fogarty and Ed Sperling - 07 Mar, 2019 - Comments: 0

A rush of new products and services promise to make the famously un-secured Industrial IoT (IIoT) substantially more secure in the near future. Although the semiconductor industry has been churning out a variety of security-related products and concepts, ranging from root of trust approaches to crypto processors and physically unclonable functions, most IIoT operations have been slow to adop... » read more

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